SAN FRANCISCODSP design tool manufacturers are increasingly backing SystemC, the C-language derivative said to support rapid ASIC and FPGA design.
New releases of Cadence Design Systems Inc.'s Signal Processing Worksystem (SPW) software and Axys Design Automation Inc.'s MaxSim Developer Suite increase support for SystemC. Both releases were on view at last week's Design Automation and Test in Europe (DATE) conference in Paris.
But DSP tool competitors like Elanix Inc. wonder whether SystemC will enable faster time-to-market than, for example, a C-code generator for general-purpose DSPs.
Based on C and C++, SystemC is the design and verification language licensed by the Open SystemC Initiative. Its advocates say SystemC lets designers move rapidly from block-level concepts to a full implementation in hardware and software.
But the SystemC spec is not thoroughly defined, said Gerry Sullivan, director of software engineering at Elanix (Westlake Village, Calif.). For time-to-market, Elanix and competitors like MathWorks Inc.'s supply C-code generators that link with Texas Instruments Inc.'s Code Composer Studio on both fixed- and floating-point versions of the TMS320C5000 and -C6000 DSPs.
While SystemC was meant to help move high-level block and algorithm simulations rapidly into working silicon, advocates inevitably couple its modeling capability with other simulators.
Version 4.8 of Cadence's SPW tools, for example, positions SystemC modeling capabilities on a checklist that includes C, C++, Verilog, VHDL, Verilog-AMS, ISS and Matlab.
"Customers can add custom blocks using SystemC," a Cadence spokesman said. "The tight connection SPW 4.8 has with SystemC 2.0 through a Block Wizard accelerates reuse of models written in an industry-standard modeling language, as well as models customers have written in SPW."
Accelerated de signs
As a result, SystemC becomes another vehicle for accelerating ASIC/FPGA designs, especially in the advanced digital communications and multimedia markets. SPW's hierarchical block-level design flow integrates with Xilinx Inc.'s Coregen tools, as well as with Cadence's AMS Designer, said Rahul Razdan, Cadence's vice president and general manager for functional verification.
Version 2.1 of Axys' MaxSim component interface similarly positions SystemC version 2.0 as yet another input to its own simulation tools allowing integration of models written in SystemC to be simulated along with those generated in C/C++. Its debug interface allows easy attachment of multiple third-party debuggers to processor and other models, Axys said at DATE.
Axys (Palo Alto, Calif.) aids DSP and ASIC development with multicore simulation and synchronous system-on-chip debugging tools, said president and chief executive officer Vojin Zivojnovic.
Axys' MaxSim Developer Suite 2.1 is shipping now and pricing starts at $9,700 per year. Cadence's SPW 4.8 is priced at $22,000 for a one-year license.