Ultra-low power 32 kHz RC oscillator designed in GlobalFoundries 22FDX
Open-Silicon Awarded Patent for Low Power ASIC Design Methodology
PowerMAX™ enables design for the lowest possible power
MILPITAS, Calif. – September 14, 2011 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has issued U.S. Patent 7,941,776 related to Open-Silicon’s PowerMAX technology. Low power SoC design is a key differentiator for not just mobile applications, but also many networking, telecom, storage, and computing solutions. This new Open-Silicon patent focuses on lowering SoC dynamic and standby power by enriching the target standard library to best fit the needs of a particular design.
Specifically, this patent encompasses the intellectual property rights of Open-Silicon’s ZenCells™, standard cells created on-the-fly using PowerMAX’s design-specific library augmentation. ZenCells drive down both dynamic and leakage power through a method of closed-loop IC design optimization via the creation of design-specific cells from post-layout patterns. This optimization process involves automatically creating design-specific cells with desired characteristics, such as power, performance, or noise, which are then implemented as a standard cell from a set of post layout patterns. The pattern represents a part of or a whole standard cell and contains information regarding the pattern, such as layout, timing area, power and noise. Because these cells are created from post-layout patterns, the risks of prior dynamic library techniques are easily avoided. The result is cells that are optimized to satisfy the constraints imposed by the design context, thus bringing powerful design-specific customization to standard cell-based design methodology.
Introduced in 2008, PowerMAX is part of Open-Silicon’s Max Technologies product line – a result of extensive R&D to create a series of products that allow customers to take their designs to a level beyond what the latest EDA tools offer. Based on a strong foundation of conventional techniques, PowerMAX adds design-specific library augmentation, back biasing, power recovery and custom leakage signoff, resulting in the ASIC industry’s most complete low power design offering. The total Open-Silicon PowerMAX offering includes both the conventional techniques and the new technologies. By combining the best industry standard methods with novel technologies unique to Open-Silicon, customers can achieve the lowest power consumption possible for their silicon.
“Increasing levels of integration in performance-driven SoCs have challenged designers to come up with novel architectural and physical design solutions for power density limitations. At the other end of the spectrum, mobile applications are driving exponential growth in mobile performance, matched with every-increasing battery life requirements,” said Colin Baldwin, director of marketing for Open-Silicon. “Open-Silicon identified this growing problem early on and developed the MAX technologies to solve it. The award of this patent underscores Open-Silicon’s commitment to low power technology, and the company’s ability to provide its customers with better custom silicon.”
About Open-Silicon, Inc.
Open-Silicon is a leading semiconductor company focused on SoC realization for traditional ASIC, develop-to-spec, and derivative ICs. In support of the industry trend towards collaborative engineering and design-lite, Open-Silicon offers SoC architecture, system design, physical design, low-level software, and high-quality semiconductor manufacturing services with one of the world’s broadest partner ecosystems for IC development. For more information, visit Open-Silicon’s website at www.open-silicon.com or call 408-240-5700.
|
Related News
- Dolphin Integration Receives Open-Silicon's Award for the Emerging IP Partner of the Year 2016 in the Low Power IoT Ecosystem
- Open-Silicon Enables Solarflare’s Low Power 10Gb Ethernet Solutions
- Innosilicon's Bitcoin ASIC powered by Samsung's Low Power FinFET technology to achieve record breaking performance
- Open-Silicon, Credo and IQ-Analog Showcase Complete End-to-End Networking ASIC Solutions at OFC 2018
- Open-Silicon to Showcase Breadth of ASIC Solutions at CDNLive 2016, Bangalore, India
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |