Operating at 1.25Gbps, Arasan’s UFS Link Layer IP is Ideal for Next Generation Mobile Storage
San Jose, California – October 21, 2011 -Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions, announced today that the company has successfully demonstrated its UFS Link Layer IP and its associated UFS Hardware Development Platform (HDP) in the Mobile Memory Workshop hosted by JEDEC and TSIA in Hsinchu Taiwan on October 12th, 2011. Arasan demonstrated its UFS 1.0 compliant UniPro® on an FPGA, running full Gear 1 speed at 1.25Gbps on a Linux system during the UFS workshop. Following this exciting demonstration, Arasan will also demonstrate its MIPI® UniPro IP, the foundation of UFS Link Layer, on its Hardware Development Platform at ARM TechCon on October 25th, 2011 at the Santa Clara Convention Center, Santa Clara, California.
Arasan’s UFS UniPro IP, based on its MIPI UniPro IP certified by UNH Lab, provides the link layer between the physical layer (PHY) and the protocol and application layers in UFS’s layered architecture for next generation high speed and high capacity mobile storage. Designed to be independent of the PHY layer, MIPI UniPro is a layered protocol for interconnecting devices and components within mobile systems such as cellular telephones, handheld computers, digital cameras, and multimedia Devices. UFS adopted MIPI UniPro to enable mobile devices, such as smartphone and UFS mobile storage devices, to utilize UFS PHY layer (i.e. M-PHY) in order to exchange data at high data rates, with low pin counts and at low energy per transferred bit.
With Arasan’s UFS Link Layer installed on two FPGA-based HDP systems (one source and one device) next to each other, Arasan demonstrated the data transfer at 1.25Gbps (or Gear 1) between the source and the destination. With UFS UniPro, in an FPGA as the heart of the system, the HDP is designed to accelerate hardware development, software development and compliance testing.
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers and optional customization services for MIPI, USB, SD, SDIO, MMC/eMMC, CF, UFS, xD and many other popular standards. Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services. Based in San Jose, CA, USA, Arasan Chip Systems has a 15 year track record of IP and IP standards development leadership.