Xilinx Enables Low Cost Ethernet-Over-Sonet Solutions: Ships IP Cores Optimized For The New Spartan-IIE FPGAs

SAN JOSE, CA--(INTERNET WIRE)--Feb 6, 2002 -- Xilinx, Inc. (NASDAQ:XLNX), announced today the immediate availability of its POS-PHY Level 3 (PL3) and Gigabit Ethernet Media Access Controller (MAC) Intellectual Property (IP) cores for use with its Spartan-IIE FPGAs. The PL3 core is compliant with the Optical Internetworking Forum (OIF) System Packet Interface (SPI) --3 specification while the Gigabit Ethernet MAC (GMAC) core is compliant to the IEEE 802.3-200 standard. With these cores, highly functional, scalable and standards-based equipment supporting the OC-48 data rates can be easily built to meet the exploding growth of Internet traffic.

"Ethernet is becoming a key technology driving the LAN/WAN convergence based on its broad industry acceptance and user familiarity," said Per Holmberg, senior product marketing manager for IP Solutions at Xilinx. "The combination of the cores and Spartan-IIE FPGAs provide system architects with the ability to quickly build cost effective and flexible solutions that can seamlessly connect newer Gigabit Ethernet systems to their existing SONET/SDH networks."

 POS-PHY Level 3 Core

The PL3 core can support bandwidth in excess of the OC-48 data rates with single or multi-channel operation. It has an asynchronous FIFO interface with configurable data bus width (8 or 32), FIFO size, burst length, and FIFO thresholds. The PL3 core has been fully verified in hardware for inter-operability with PMC Sierra PHY devices S/UNI 2xGE.

 Gigabit Ethernet MAC core

Ideally suited for the development of Gigabit communications and storage equipment, the GMAC core incorporates an 8-bit Gigabit Media Independent Interface (GMII) running at 125 MHz to provide up to 1 gigabit per second (Gbps) total bandwidth. Additionally, the core supports single-speed half and/or full-duplex operation and is fully compliant to the IEEE 802.3-2000 standard specification. Further, it provides support for VLAN frames and JUMBO frames (up to 9000 bytes in length) as well as optional network management features including statistics gathering and flow control. It can be configured and monitored through a processor-independent interface, providing designers with the flexibility to choose the most ideal processor for a given application.

 License price and availability

Both cores are available now as LogiCORE(TM) products under the terms of SignOnce IP license and downloadable over the web at www.xilinx.com/ipcenter. The GMAC core is priced at $16,000 and the PL3 core at $9,995. In addition to support for the newest Spartan-IIE family, these cores also support Xilinx®, Virtex®-E and Virtex-II family of FPGAs using the latest ISE 4.1i version of the Xilinx design software. For more information about Xilinx Spartan solutions, visit www.xilinx.com/spartan.

 About Xilinx

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as intellectual property cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, low-power portable and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.