Stratix V GX FPGA Hard PCIe Gen3 Blocks Ease Development of PCIe Gen3-Systems
San Jose, Calif., December 13, 2011—Altera Corporation (Nasdaq: ALTR) today announced it has successfully interoperated its 28-nm Stratix® V GX FPGA with PLX® Technology's (Nasdaq: PLXT) ExpressLane™ PCI Express® (PCIe®) Gen3 switch. Stratix V GX FPGAs feature hard PCIe Gen3 IP blocks and are the only FPGA shipping today that interoperate with a PCIe Gen3 switch.
"Interoperating the industry's highest-performance 28-nm FPGA with the industry's first PCIe Gen3 switch saves significant development time by enabling customers to focus on design issues rather than verifying electrical compliance between devices," said Patrick Dorsey, senior director of component marketing at Altera. "The hard PCIe Gen 3 IP blocks in Stratix V conserve logic resources, while increasing throughput and reducing power consumption for high-performance, leading-edge applications."
Stratix V FPGAs feature up to four hard PCIe Gen3 x8 IP blocks. The PCIe Gen3 IP blocks support x1, x2, x4 and x8 lane configurations and provide transfer rates up to 8-Gbps per lane, sustaining 2X higher throughput using Gen3 x8 lanes compared to the previous Gen2 x8 version. Hardening the PCIe IP blocks in Stratix V FPGAs delivers a savings of over 100,000 logic elements when compared to alternative soft implementations. The hard PCIe Gen3 IP blocks embed the PCIe protocol stack into the FPGA and include the transceiver modules, physical layer, data link layer and transaction layer. Stratix V FPGA's PCIe Gen3 IP targets PCIe Base Specification Rev. 3.0, 2.x, and 1.x.
"Interoperation with Stratix V GX FPGAs and PLX PCIe Gen3 switches is critical in the development of the ecosystem and we are pleased to see leaders like Altera developing Gen3 products," said David Raun, vice president of marketing and business development at PLX. "Having launched the industry's first PCIe Gen3 silicon in 2010, and remaining the only company shipping production-ready Gen3 switches today, PLX is well-prepared to service this rapidly expanding market."
PCIe Gen3 is the latest version of the industry's most popular high-speed interconnect technology, and PLX switches blend valuable innovation and high port counts to enable new, more powerful designs in servers, storage and communications platforms. The PLX Gen3 portfolio includes 11 devices ranging from 12 to 48 lanes and three to 18 ports with more configurations in development. All devices are available today from PLX.
Altera's 28-nm Device Portfolio—Tailored for Specific Design Needs
Altera's 28-nm FPGA portfolio is the industry's most comprehensive set of devices tailored to meet the customer's diverse design requirements. The portfolio provides customers with clearly differentiated solutions across its Arria® V, Cyclone® V, and Stratix V FPGA families and its HardCopy® V ASIC family. By investing in process technology, architecture, transceiver technology and hard intellectual property (IP) blocks, the portfolio enables designers to meet their unique cost, performance, and low-power needs with less time and effort. For more information on Altera's 28-nm product portfolio, visit www.altera.com/28nmportfolio.
Pricing and Availability
Stratix V FPGA are currently shipping. The high-performance 28-nm devices are used by customers who require the highest performance and latest technologies, including 14.1 Gbps transceivers, embedded HardCopy blocks and variable precision DSP blocks. For additional information on PCIe technology see http://www.altera.com/technology/high_speed/protocols/pcie-hard-ip/pro-hard-ip.html. For additional information about Stratix V FPGAs, visit www.altera.com/stratix5. For information about pricing, contact your local Altera sales representative.
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.