TSMC goes it alone with 3-D IC process

Rick Merritt, EETimees
12/13/2011 2:51 PM EST

BURLINGAME, Calif. – TSMC will try to go it alone with an integrated 3-D chip stacking technology as its only offering for future customers. The approach makes commercial sense for TSMC, but some fabless chip designers said it lacks technical merit and limits their options.

3-D chip stacks are seen as a strategic new direction in chip design at a time when progress is becoming more difficult in the traditional scaling of semiconductor process technology. However, foundries, packaging houses and integrated chip makers are still debating how to address the technical challenges making 3-D stacks.

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