WILSONVILLE, Ore., April 3, 2002 - Mentor Graphics Corporation today announced that the LBISTArchitect™ tool has been successfully used to implement logic built-in self test (BIST) for the ARM966E-S™ microprocessor core.
Mentor's LBISTArchitect tool aids in reducing test costs by adding a small test controller that self-tests embedded cores or integrated circuits (IC). As a result, an embedded core can be tested to a guaranteed fault coverage wherever it may be instantiated, regardless of the available pin access of the target IC.
BIST tests a chip's circuits without using external patterns, effectively resulting in a chip that can test itself. Logic BIST was successfully implemented on the ARM966E-S core using LBISTArchitect. The ARM966E-S processor is a full scan core with test coverage that exceeds 99 percent with ATPG. The Design-for-Test (DFT) group at ARM found the LBISTArchitect tool and methodology easy to use for implementing BIST. ARM established that the silicon area needed to be dedicated to Logic BIST itself was less than 5 percent of the total area of the core and that test coverage for the microprocessor core was in excess of 95 percent.
"We are pleased to have this opportunity to work with an industry leader such as ARM. Mentor's LBISTArchitect delivered the ease of use and high test coverage ARM needed when they implemented BIST and verified their synthesizable ARM966E-S core," said Stephen Shostek, Logic BIST Business Unit Manager, Mentor Graphics. "Logic BIST plays a central role in enabling Test-Ready intellectual property (IP) since the test can be built in from the beginning. Developers of System-on-Chip devices are under increasing pressure to keep physical characteristics, such as die size and power consumption to a minimum. This pressure creates an increasing demand for more efficient and easy to use DFT tools such as LBISTArchitect."
"ARM continues to evaluate test methodologies to accommodate our Partners' present and future test needs. The successful implementation of the Mentor LBISTArchitect tool on the ARM966E-S core adds another possible solution for ARM partners with SoC hierarchical capabilities," said Teresa McLaurin, Design for Test manager, ARM.
Mentor's LBISTArchitect is a complete DFT product for implementing logic BIST in a design. The product contains patented BIST-ReadySM technology that ensures fault coverage comparable with leading-edge automatic test pattern generation (ATPG) tools without the timing, routing and power dissipation overheads traditionally seen in BIST. LBISTArchitect's design rules checks can be run at any stage of the design and test process, and combined with the parameterizable BIST controller, ensure that the test and BIST implementation can handle engineering change orders (ECOs) without the need for re-synthesis. LBISTArchitect can be completely integrated with the Mentor Graphics® FastScan™ ATPG and BSDArchitect™ New Edition boundary scan synthesis products for a complete DFT solution.
ARM carried out this project to determine the feasibility of implementing Logic BIST on its sythesizable cores using commercially available tools.
For more information regarding LBISTArchitect and the complete portfolio of Mentor Graphics ATPG, BIST, scan and new embedded deterministic test products, please visit the Mentor Graphics Design-for-Test Web site at www.mentor.com/dft.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 3,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.