Henderson, NV – January 23, 2012 – Aldec, Inc., announces the release of ALINT 2012.01,a design rule checking application for HDL-based FPGA/ASIC designs. The new release adds documentation support addressing the strict guidelines placed on various safety-critical industries such as DO-254 for avionics, IEC 61508/61513 for nuclear and ISO 26262 for automotive. The latest release extends the Exclusion Management mechanism, enabling the ability to specify “irrelevant” coding standard violations and justify any specified waivers from within the industry.
“The ability to generate a report with complete analysis of detected violations and justification of waivers is of paramount importance and can help engineers decrease the effort in documentation and reporting,” said Louie De Luna, DO-254 Program Manager.
Fully integrated with the Violation Viewer and reporting engine, the new Exclusion Management mechanism facilitates the desirable practice of creating quality design artifacts essential to obtaining compliance with the requirements outlined in the various safety-critical design assurance standards. The standalone reports may include both relevant and irrelevant coding standard violations and could be viewed on any standard web browser independent of ALINT. The reports allow for navigation through the design hierarchy, coding standard violation analysis, and cross-probing from the violation to the source files providing complete visibility into the quality of design at that point in the development cycle.
ALINT 2012.01 with support for VHDL or Verilog DO-254 design rule plug-in is available today and is sold directly from Aldec and its authorized world-wide distributors.
For additional information about ALINT for safety-critical, including downloads and presentations, please click here.
Reviewing another designer’s code presents a substantial task – sorting through endless screens while trying to catch every violation against strict company coding standards. For this reason, today’s designers rely on automatic tools for analysis, such as ALINT, and then opt to address coding standard violation reports instead of analyzing the sources themselves. This approach, also known as “linting”, dramatically reduces the cost of a typical review by minimizing the manual labor required.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com