By David Larner, Embedded Systems
November 1, 2001 (9:00 a.m. EST)
Mentor Graphics introduced v5.2 of its FPGA Advantage HDL design flow for creation, management, simulation and synthesis of FPGA designs.
The new version has features that improve design creation and design reuse, and synthesis enhancements that generate more accurate timing data. To speed importation of legacy code into a new design, there is a recursive file search feature that can set up and search through a directory of IP. Mentor's TimeCloser synthesis technology has been extended to deal with Altera's Quartus-II design environment. V5.2 is available now.
Mentor and Altera have joined each others partnership programmes. Altera became the seventh member of Mentor's Embedded Technology Adoption Program (ETAP). Altera will now give its embedded design customers access to an enhanced version of the Mentor's XRAY Debugger. Mentor's Embedded Software Division is also a founding member of Altera's newly created Excalibur Partner Program.
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