English
Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Juniper Networks Adopts Jasper Formal Technology to Mitigate Design and Verification Risk
Mountain View, Calif, - February 7, 2012 -- Jasper Design Automation, the leading provider of verification solutions based on formal technology, today announced that Juniper Networks has adopted JasperGold® formal technology for verification and design flows. “We selected Jasper’s solutions because of the clear advantages their tools and products offer over other options,” said Sanjeev Kumar, ASIC senior manager at Juniper Networks. “We quickly recognized the value and quality improvements that Jasper’s unique formal products can bring to our high-performance network products.”
Juniper was able to load in its design, write properties, and begin using Jasper’s unique formal techniques quickly. The Jasper Visualize™ feature allowed Juniper to thoroughly comprehend designs and swiftly correct any errors that were found.
“Being able to visualize RTL early in the design cycle, even without a need for a testbench, was key to our decision,” added Kumar. “The remarkably intuitive and easy-to-use interactive debugging capabilities that Jasper provides will allow us to speed up design exploration and thus reduce design errors and market timing risks.”
“Juniper’s adoption of our products is a testament to the time-to-market benefits that our solutions offer,” said Kathryn Kranen, President and CEO of Jasper Design Automation. “We look forward to partnering with Juniper to make Jasper formal technology a standard part of their design and verification flow in the future.”
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics. Jasper technology has been an integral part of over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks, increase design, verification and reuse productivity; and accelerate time to market.
|
||||||
Related News
- Codasip adopts Siemens' OneSpin tools for formal verification
- Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development
- Jasper Launches Security Path Verification App - Industry's First Formal Solution for Detecting Security Vulnerabilities in SoC Designs
- Jasper and Duolog Partner to Combine SoC Integration with Formal Verification
- Jasper Makes Formal Verification Power-Aware with a New Low Power App for Verification of SOCs with Multiple Power Domains
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
|
E-mail This Article | 
|
|
Printer-Friendly Page |