Accellera Systems Initiative Announces IEEE 1666 SystemC Language Standard for Electronic System-Level Design Is Available for Download at No Charge
SystemC supports efficient, high-level design of complex Integrated Circuits and Systems-on-Chips
Napa, Calif., USA, 21 February 2012—The Accellera Systems Initiative™ announced today that the IEEE Standards Association (IEEE-SA), a globally recognized standards-setting body within the IEEE, now offers the latest version of the IEEE 1666™ "Standard SystemC Language Reference Manual," for download at no charge, as part of the IEEE Get program.
Announced by the IEEE-SA in November 2011, the revised version of the IEEE 1666 specifies the SystemC™ standard, a high-level design language used in the design and development of electronic systems. The new version encompasses many enhancements, notably support for Transaction-Level Modeling (TLM), a critical approach to enable high level and more efficient design of complex ICs and SoCs.
Beginning immediately, companies, universities, research institutions, and individuals worldwide can freely access the standard and develop applications for SystemC-based tools and technologies. The IEEE 1666 is available as a PDF formatted document. To download a copy, please visit http://standards.ieee.org/about/get/index.html#get1666.
“We continue to work with the IEEE to make approved EDA and IP standards available,” said Shishpal Rawat, chair of Accellera Systems Initiative. “Through the IEEE Get Program, we provide valuable standards documentation at no cost to the worldwide electronics industry community to support and foster electronic design innovation.”
“Systems designers and architects are faced with complex challenges that are a hybrid between hardware and software," said Judith Gorman, managing director of IEEE-SA. "The sheer complexity of today’s SoCs and the demand for IP reuse make the need for standardized interoperability, collaboration and exchange of information a necessity to promote innovation. Through our ongoing Get Programs, electronic industry stakeholders can freely access the latest versions of popular standards like IEEE 1666.”
In December 2011, Accellera™ and the Open SystemC Initiative™ (OSCI™) merged to form Accellera Systems Initiative. The new organization leverages the complementary efforts of both organizations and is chartered to create comprehensive system-level and semiconductor design standards to benefit the electronic design community by facilitating efficient collaboration among its worldwide members.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development, and as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. For membership information, please email membership@accellera.org.
|
Related News
- IEEE Approves Revised IEEE 1666 "SystemC Language" Standard for Electronic System-Level Design, Adding Support for Transaction-Level Modeling
- New SystemC Library Now Available from Accellera Systems Initiative
- IEEE Ratifies SystemC 2.1 Standard for System-Level Chip Design; IEEE(R) 1666 Allows Faster System-on-Chip Design, Intellectual Property Exchange
- Accellera Systems Initiative advances the SystemC ecosystem with a new core language library
- Accellera Systems Initiative completes SystemC AMS 2.0 standard for mixed-signal design of electronic systems
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |