Tensilica Baseband DSPs and Dataplane Processors (DPUs) Power LTE/HSPA/3G Multimode Modem IC from NTT DOCOMO, Fujitsu, NEC, and Panasonic Consortium
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
HiFi Audio DSP Also Integrated in Modem for Voice Processing
Barcelona, SPAIN – February 27, 2012 – Tensilica®, Inc. today announced that the second-generation multi-mode LTE/HSPA/3G (Long Term Evolution) baseband chip design announced last week by NTT DOCOMO features multiple Tensilica dataplane processors (DPUs), including the HiFi Audio DSP (digital signal processor) and the ConnX BBE16 Baseband DSP. As with the first generation NTT DOCOMO-sponsored design now shipping in volume in cell phones and tablets, this chip was co-developed by industry leaders Fujitsu, Panasonic and NEC.
“NTT DOCOMO has been an important partner, and we are very excited about this second-generation design, which reduces the power dissipation through multi-standard integration and incorporates even more key functions for next-generation smartphones and tablets such as TD LTE,” stated Eric Dewannain, Tensilica’s vice president and business unit manager, baseband business unit.
First general LTE smartphones, tablets and dongles incorporating Tensilica DPUs were introduced starting at the end of 2010 and include Fujitsu’s ARROWS X LTE F-05D Smartphone and ARROWS’ Tab LTE F-01D tablet. More LTE-based smartphones, tablets and dongles powered by Tensilica are being introduced at the Mobile World Congress show in Barcelona. NTT DOCOMO is the leading mobile phone operator in Japan and also has a strong presence internationally.
About Tensilica
Tensilica, Inc. is the leader in dataplane processor IP cores. Dataplane processors (DPUs) are a superset of DSPs and CPUs that can scale from tiny micro signal processors to programmable offload accelerators and powerful DSPs. DPUs deliver 10 to 100x the performance because they can be optimized using Tensilica’s automated design tools to meet specific and demanding signal processing performance and efficiency targets. Tensilica’s DPUs power SOC designs at many Tier 1 system OEMs and seven out of the top 10 semiconductor companies for designs in mobile wireless, telecom and network infrastructure, computing and storage, and home and auto entertainment. For more information on Tensilica’s patented, benchmark-proven DPUs visit www.tensilica.com.
|
Related News
- Tensilica Announces Availability of Atlas Reference Architecture Dataplane Processors for a Complete Baseband PHY for LTE, HSPA+ and WiMAX
- Multiple Tensilica IP Cores Power NEC, Fujitsu and Panasonic Mobile Communications Fully Functional LTE Handset SOC for Major Japanese Wireless Carrier
- Blue Wonder Communications to Develop LTE Baseband IP Using Multiple Optimized Tensilica Dataplane Processors
- Fujitsu Laboratories Implements Custom Processor for 3G/LTE Modem with Synopsys' Processor Designer
- Fujitsu Signs Multi-Year Corporate License for Tensilica's Audio, Baseband DSP and Dataplane Processor IP Cores
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |