Barcelona tips analog IP 'engines'
Barcelona tips analog IP 'engines'
By Stephan Ohr, EE Times
April 8, 2002 (4:29 p.m. EST)
SAN FRANCISCOBarcelona Design Inc. will introduce this week a new series of modeling "engines" said to represent the kernels for synthesizable analog intellectual property. The engines, which will include detailed process and topology models for a variety of analog functions, can be used with a scalable "synthesis platform" to place and route an analog IP within a system-on-chip design.
The distribution of the IP engines shifts Barcelona from a focus on EDA tools and methodologies to a vendor of analog IP. Peter Santos, Barcelona's vice president of marketing and business development, said the company was "refocused" with $25 million in third-round venture funding from Sequoia, Foundation and Crosslink and by the ascension of Thomas Heydler as chief executive officer.
The entire business plan, in fact, is still meant to address the shortage of analog engineers. Large IC houses like Int el, Texas Instruments and STMicroelectronics still look to customize analog circuits for their system-on-chip (SoC) designs. But because it is so tied to process technology, analog circuitry does not lend itself to the kind of abstraction with which digital circuits can be manipulated. A trial-and-error approach to phase-locked-loop (PLL) circuitry can take three to six months out of the design cycle, said Santos. And today's analog IP provider must practically ship an engineer with each piece to help solve problems and complete the integration.
Barcelona's approach is to ship "solvers" instead of engineers with analog IP. Its new product line has two types of products: a series of engines, which are synthesizable (process-specific) models of analog circuit functions, and a synthesis platform, which combines an optimizer and router to output an analog circuit in a variety of forms. As a Verilog behavioral model, the output of the platform can be tried out on a larger SoC; a netlist allows the circui t to be used in full-chip verification runs; and the GDSII output is the manufacturing blueprint.
The engines and synthesis platform use the same fast but highly accurate modeling technology Barcelona developed for its online simulation tools. The technology, called geometric programming, can capture analog transfer functions with the GPP+ language. Unlike Spice, Verilog-AMS or any of the simulators before it, geometric programming can solve matrix equations with a huge number of variables. The company's Prado synthesis platform can resolve a 220,000 x 220,000 matrix in a couple of hours, Santos said.
The first engine available part of the company's Miro class of products is a PLL manufacturable on the 0.18-micron CMOS process of foundry Taiwan Semiconductor Manufacturing Co. The PLL engine, the CGS18T, models seven process and temperature corners; the IP captures signals from 10 MHz to 2 GHz and outputs divisible clocks and data (with le ss than a 40-picosecond jitter window). In TSMC's 0.18-micron process, the device is smaller than 0.5mm2 and consumes less than 5 milliwatts from a 1.8-volt supply.
Engines in the Miro family will include PLLs and clock generators in other foundry processes and geometries, Santos said. The company now issues two engines per quarter, but Santos expects that to ramp quickly with demand. Additions to the product line will include op amps, data converters and RF components like inductors, resonators and low-noise amplifiers. Users will be charged for the "finished instances" placed and routed GDSII files, netlists and pinouts Santos said.
Copyright © 2003 CMP Media, LLC | Privacy Statement