ANDOVER, Mass.--March 23, 2012--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its DDR-Xactor verification IP providing DDR and LPDDR memory models and a complete DFI-PHY verification solution.
DDR-Xactor VIP includes:
- SDRAM memory chip and DIMM models
- DFI-PHY model
- Simple AXI-based memory controller model
- Compliance testsuite
- Timing and protocol checks
- DFI and JEDEC protocol analyzer trackers
Models and compliance testsuites are developed in SystemVerilog and support UVM, OVM, and VMM environments.
Memory models support all speed modes and configurations including parameter files for the major SDRAM vendors including Samsung, Hynix, Micron, and Elpida. Memory models support a full SDRAM/DIMM user API with many advanced features not included in many “free” models such as:
- Clock jitter
- Random DQS timing
- CRC/parity error injection
- Backdoor access to DDR chip and DIMM memory locations
- Callbacks and analysis ports for memory access and state transitions
DFI-compliant PHY verification is performed using the Avery provided plug’n’play testbench and compliance testsuite focusing on DFI functional requirements such as reset, write leveling, refresh, power down, frequency change, and PHY update.
SoC/memory controller verification is performed using the Avery DDR chip/DIMM memory models to test memory controller functions such as memory refresh and control modes such as DDR4's PDA and modereg readout.
DDR-Xactor supports the JEDEC SDRAM standards including DDR4 (version 0.9) and DDR3, the JEDEC mobile memory standards including LPDDR3 and LPDDR2, and DRAM module standards. DDR-Xactor also supports the DFI-PHY 2.1 and 3.0 standards.
“As DDR4 adoption ramps up, chip companies will need to upgrade their SoC architectures with new memory controller IP and DDR PHY IP by either making or buying new IP. Avery is in a position to provide these companies the verification solution for this memory controller and PHY development as well as overall SoC verification,” says Chilai Huang, president of Avery Design Systems.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, X verification, and RT-level DFT at-speed testability analysis; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, and MIPI standards; and scalable distributed parallel logic simulation. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.