Actel has quietly signed deals with specialist intellectual property (IP) suppliers as a back-up in case its in-house IP for embedded programmable logic does not turn out to be the one demanded by asic designers in the future.
The company is not expecting big sales of programmable logic that can be embedded into asics for some time, according to John East, president and CEO.
"We are finding the market very slow to develop," he said. "All the IP segments are doing badly. Only ARM is doing well. And the market may not be ready for [embedded FPGA]."
The company has developed an IP core that focuses on general-purpose logic, in contrast to offerings from some start-ups, such as UK-based Elixent, which have homed in on accelerating digital signal processing (DSP) functions.
"We designed a very generic FPGA with a focus to make it small and cheap," said East. "The packing density of FPGAs is so much worse tha n asic gates that you really have to know what you want and minimise the size.
"Our initial evaluation was that [logic] cost would be everything. But you can come up with an FPGA which is aimed at arithmetic."
He adds that future asic designs may prize DSP efficiency above that for random logic, but that Actel does not plan to launch a second internal design project.
"We have relationships that we can use for that. We have not announced those agreements as yet," said East.
Actel says it has overcome the yield problems it suffered with its flash-based FPGAs. But the company will not attempt to use the technology to displace its antifuse-based products, despite a resistance to one-time programmable (OTP) devices or high-end SRAM-based FPGAs.
John East, president and CEO, said: "Nobody really wants a volatile solution. But, with flash, we still have decisions to make. More and more it is true that you have to give up something to get somethin g.
"Speed is a matter of choice. You could make a fast flash family. We have opted for ProASIC+ to be not super-fast but price-conscious."
The high-speed arena will be the focus for a forthcoming antifuse family, although the size will be limited by the practical cost of OTP devices.
"As cost goes up, people are less amenable to OTP. We won't target to have the world's biggest FPGA," said East. "For ProASIC+, we have changed foundries and made a better job of making it work on a memory process. The yields are now very good.
"For our [first] flash FPGAs, we had to have a custom flash process. It is typical when you bring up a new process that you have yield problems. It took two years longer to get there, but now we are there."