Product offer designed to enable continued advances in performance and efficiency of mainstream mobile consumer devices
Bernin, France and Peabody, Mass. – April 16, 2012 – Soitec (Euronext), a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, announced today its fully depleted (FD) product roadmap comprising two products designed for both planar and three-dimensional (FinFET) approaches to building transistors. Available now, FD wafers from Soitec, pre-integrate critical characteristics of the transistor within the wafer structure itself. Soitec’s FD wafers offer an early, low-risk migration at the 28nm node down to 10nm and beyond, lowering costs and enabling significant advances in the performance and power efficiency of mobile devices such as smartphones and tablets. Soitec also announced research and other activities dedicated to further boosting transistor performance, both silicon-based and with new materials.
Soitec’s product lines support the industry’s FD International Technology Roadmap for Semiconductors (ITRS), speeding time-to-market and lowering chipmakers' overall manufacturing costs.
Soitec’s FD-2D product line enables a unique planar approach to fully depleted silicon technology as early as the 28nm node, in which chipmakers can continue to leverage their existing designs and process technologies. FD-2D also enables immediate gains in performance and energy efficiency for mobile and consumer multimedia chips. The company’s FD-3D product line facilitates the introduction of three-dimensional (FinFET) architectures with reduced time and investment, and drives substantial simplifications in the transistor fabrication process, targeting nodes below 20nm.
“Our fully depleted product roadmap addresses the critical needs of the semiconductor industry and solves key challenges facing manufacturers today. Whichever path chip vendors choose to follow – planar or FinFET – Soitec provides solutions that address cost, performance, power-efficiency and time-to-market issues,” said Paul Boudre, chief operating officer of Soitec. “FD-2D enables immediate and significant performance leaps, while FD-3D makes FinFET a reality for the entire industry at accelerated schedules and reduced risk.”
Soitec’s proprietary Smart Cut™ layer transfer technology is leveraged to generate thin layers with high quality and uniformity, bringing the ability to tune starting wafers to successive technology nodes and delivering key advantages as chip manufacturers pursue the best performance, efficiency and manufacturability results. By predefining critical characteristics of the transistor, these wafers enable efficient implementation and manufacturing. Specifically, they feature a high-quality top silicon layer over a buried isolation layer – these two layers are carefully optimized to predefine the geometry and electrical isolation of transistors, enabling suppression of process steps and simplification of the CMOS fabrication process, opening new usage opportunities and providing a lower-cost solution.
The FD-2D Product Line – Next-Generation Power Efficiency and Performance, Now
The top silicon layer of Soitec’s FD-2D wafers is ultra-thin and ultra-uniform, making it possible to achieve planar fully depleted transistors with a silicon thickness that may be as low as 5nm under the gate. Between this top layer and the underlying silicon base is an ultra-thin layer of buried oxide (BOX), initially at 25nm thick. Future generations can leverage even thinner BOX layers down, to 10nm thick, providing a path for planar transistor scalability down to 14nm for mobile devices. Silicon thickness uniformity in volume production of planar fully depleted technology is critical for best results. Soitec’s FD-2D wafers have a top silicon thickness that is controlled to within just a few atomic layers. Leveraging the inherent accuracy of Soitec’s Smart Cutprocess, silicon uniformity across a full 300mm-diameter wafer can be as good as 3.2 Angstroms – that’s approximately equivalent to controlling the thickness of a surface to within 1mm over a range of 1,000km, or 0.07 inches over a range of 1,000 miles.
Planar FD transistors are built flat on the silicon, as has been the case for decades. This offers a smooth path to fully depleted technology with the first sample ICs expected at the end of 2012. The planar approach lets designers keep the same methodologies and design tools used in conventional planar technology with a straightforward path for design and IP porting. Manufacturers use the same fab tools and production lines, and extremely similar process steps. At 28nm, compared to conventional technology, the energy consumption of chips can be reduced by up to 40 percent, and the maximum operating frequency of the processors these chips embed can be improved by 40 percent or more with design optimizations. In particular, the technique known as back-biasing is extremely well suited to the planar FD architecture, thus offering designers additional means to further enhance the performance and power advantages. In addition, exceptional performance is maintained at very low power supply (sub-0.7V), enabling ultra-low-power operation in many use cases. The FD-2D wafer delivers all the power and performance benefits while enabling lower costs at the chip level for high volume mobile applications.
The FD-3D Product Line – Simplified FinFET Manufacturing
The top layer of Soitec’s FD-3D wafers is a thin layer of silicon over a buried oxide layer with a thickness defined according to customers’ needs. The silicon top layer predefines the fin height and the BOX layer provides built-in intrinsic isolation. Compared to using conventional bulk silicon starting wafers, FD-3D results in fewer challenging steps in the FinFET fabrication process, driving lower capital expenditures and operating expenses, higher production throughput and, ultimately, lower cost. In addition, these benefits translate to shorter process development learning cycles, fewer industrialization challenges and faster time to market for FinFET technology into the mainstream foundry market. Experts estimate FD-3D substrates offer a potential gain of as much as one year with respect to the trajectory possible using conventional bulk silicon substrates. The benefits of predefining fin height and isolation at the substrate level translate to better manufacturability and less process variability, leading to better overall performance at the chip level.Looking Further into the Roadmap
Soitec also is working actively to research new ways to further boost transistor performance, both silicon-based and with new materials. To continue pushing the performance of silicon CMOS, Soitec will add “strained silicon” to both its FD-2D and FD-3D product lines, with pre-production expected no later than 2014. With this solution, the crystalline structure of the silicon layer, in which transistors will subsequently be built, is modified by Soitec during fabrication of the starting wafers. This results in significantly improved electron mobility and higher maximum operating frequency for the transistors and circuits.
Looking further, several new CMOS technology options are being researched in the semiconductor industry for introduction beyond the 14nm node. The main candidates include incorporation of high-mobility materials such as germanium or III-V materials, as well as new transistor architectures such as nano-wires. Soitec is actively engaged in different R&D programs and has a number of joint development programs with partners to enhance its product lines and propose the best products to meet the needs of the industry.
Finally, Soitec is also anticipating the transition from 300mm to 450mm wafers through in-house and collaborative R&D programs to support the industry roadmap. Both the FD-2D and FD-3D offerings are fully scalable to 450mm.
Soitec is an international manufacturing company, a world leader in generating and manufacturing revolutionary semiconductor materials at the frontier of the most exciting energy and electronic challenges. Soitec’s products include substrates for microelectronics (most notably SOI: Silicon-on-Insulator) and concentrator photovoltaic systems (CPV). The company’s core technologies are Smart Cut™, Smart Stacking™ and Concentrix™, as well as expertise in epitaxy. Applications include consumer and mobile electronics, microelectronics-driven IT, telecommunications, automotive electronics, lighting products and large-scale solar power plants. Soitec has manufacturing plants and R&D centers in France, Singapore, Germany, and the United States. For more information, visit: www.soitec.com.