Synopsys Releases OpenVera 2.0 Language With New Assertions

OpenVera 2.0 Incorporates Intel's ForSpec Language and Gains Tool Support from Electronic Design Automation (EDA) Vendors

MOUNTAIN VIEW, Calif., April 15, 2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today announced the availability of OpenVera™ 2.0, with new additions to OpenVera assertions based on Intel's ForSpec language. OpenVera 2.0 combines the strengths of the OpenVera hardware verification language with Intel's newest formal verification language, ForSpec, to deliver a more comprehensive, open source hardware verification language to the verification community. The combined technology enables OpenVera users to leverage next-generation functional verification methodologies by providing one common language for writing assertions and formal properties. The addition of new assertions in OpenVera 2.0 marks a significant step forward in achieving OpenVera's objective of easing the verification bottleneck by enabling the development of a complete solution around an open, non-proprietary hardware verification language.

"Intel has many years of experience developing formal verification languages. ForSpec, our newest language, is being used by several of our processor and chipset projects," said Greg Spirakis, vice president of Design Technology at Intel. "By working with Synopsys, we are bringing our formal verification technology into an open source environment. We believe in open source standards and work with EDA vendors to bring out tools to support such a standard."

"Our collaboration with Intel is an example of how the EDA community can quickly improve the OpenVera standard," said Manoj Gandhi, senior vice president and general manager, Verification Technology Group at Synopsys, Inc. "At Synopsys, we are committed to providing an open source, state-of-the art hardware verification language for the whole user community."
 

Assertions Save Time

Assertions are statements used to specify design behavior. These statements are used interchangeably as monitors to detect incorrect design behavior in dynamic simulation or as properties to be proven exhaustively using formal verification. OpenVera assertions can be used to succinctly describe design specifications, minimizing the amount of code a user needs to write. With clear specifications and less code, verification is more productive. With the addition of Intel's ForSpec language, OpenVera 2.0 has been extended to provide language features for formal and hierarchical verification and to support a wider array of design styles with asynchronous resets and complex clocks. OpenVera 2.0 has been architected to deliver the best performance for use in both dynamic simulation and formal verification, enabling assertion-based verification for today's complex SoC designs.
 

Vendor Support is Growing

 @HDL, an EDA vendor in San Jose, California, plans to support OpenVera 2.0 with new assertions in its @Verifier product. "@Verifier is an automatic formal model-checking tool that incorporates Adaptive Functional Verification techniques," said Badru Agarwala, president and CEO of @HDL. "We plan to automatically generate OpenVera assertion-based properties for designs and also formally prove user-written OpenVera assertion properties. OpenVera assertions are well suited to support our hybrid solution that combines the benefits of model checking and dynamic simulation."

"OpenVera assertions are rich and powerful for writing properties," said KC Chen, chief technology officer at Verplex Systems, Inc. "We plan to process user-defined assertions in OpenVera to verify complex functional behavior with our BlackTie functional checker."

"The emerging assertion-based methodologies are crucial for complex IC and SoC design. Designers need seamless operations across HDLs, testbench code and assertions," said Scott

Sandler, president and CEO, Novas Systems. "That is why we are expanding our debug technology to support assertions and are working with Synopsys to integrate OpenVera assertions with our Debussy debug system."
 

How to Access OpenVera 2.0

 SoC design teams, verification teams and EDA developers can access OpenVera 2.0 by downloading the Language Reference Manual (LRM) from the OpenVera web site at www.open-vera.com. There are no licensing fees for OpenVera and access to the language and documentation is unrestricted, subject to the OpenVera license. Synopsys serves as the managing entity of OpenVera and coordinates the language development. Developers may contribute to the language and may use it to create complementary tools.
 

About OpenVera

 OpenVera is an open source hardware verification language developed specifically to meet the unique requirements of functional verification. The language enables users to describe the target application environment, including complex protocols and data objects, at a high level of abstraction, which dramatically increases productivity, readability and reusability. The latest OpenVera developments will be featured at the Ninth semiannual Synopsys EDA Interoperability Developers' Forum in Sunnyvale, CA on Tuesday, April 16, 2002. For more information on OpenVera, visit www.open-vera.com.
 

About Synopsys

 Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
 
 

Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners