Complete Test Environment Speeds Verification of Smart Card Protocol Designs
SANTA CLARA, California, April 15, 2002 – Integnology Corporation, a leading design and verification service company, today announced the availability of a powerful new ISO7816-3 Smart Card Interface (SCI) OpenVera™ verification intellectual property (IP) solution that dramatically reduces the chip-level functional verification time for designs that incorporate SCI protocols.
"We have expertise in verifying complex wireless and networking products," said Basheer Janjua, chairman and CEO at Integnology Corporation. "Now with advanced verification methodologies we can achieve the same accuracy with improved efficiency. Smart Card clients can now build comprehensive test cases for their interface design within hours of incorporating our SCI OpenVera verification IP into their testbenches, saving months of effort they would otherwise spend creating them from scratch."
The Smart Card Interface verification IP offering is a complete test environment to verify SCI's compliance with ISO7816-3. The OpenVera verification IP offers highly programmable and extendable stimulus generation, automated response checking, and test coverage measurement capabilities. The SCI verification IP architecture is based on Synopsys' OpenVera model architecture guidelines and contains built-in flexible facilities and functions that support the host interface data transfers.
"Charter OpenVera Catalyst Program members, such as Integnology, are rapidly filling the need for verification IP for numerous applications," said Jim Watts, OpenVera program manager at Synopsys, Inc. (Nasdaq:SNPS) "Integnology's Smart Card Interface verification IP solution enhances the growing portfolio now available to the OpenVera community."
Highly Productive Verification Technology
The technology in the SCI verification IP is much more than a simple interface simulation model. The new technology embeds protocol knowledge and advanced verification techniques in an easy-to-use reusable block. The SCI verification IP raises the level of productivity of verification engineers by providing a pre-verified interface stimulus generation and automated response checking component that leverages the power of Synopsys' VERA® testbench environment. With this technology, engineers can quickly assemble a verification environment for complex interface designs and immediately focus on their primary goal of writing customized test cases that verify their specialized designs.
"By helping customers implement verification projects over the years, we have built our expertise in verification for complex designs, especially using the VERA testbench solution," said Jen Silverstein, Ph.D., director of marketing and business development at Integnology. "The SCI verification IP is a combination of our domain knowledge and the high productivity realized from use of the OpenVera language. With the SCI verification IP, engineers will be able to quickly test the functionality of interface design and subsequently improve the design."
SCI verification IP features include:
- ISO/ IEC 7816-3 compliant, comprehensive verification environment.
- Architecture provides functional facilities for the host-side data transfers.
- Coverage for all phases of card transactions including; card activation, ATR sequence, character receive and transmit, block receive and transmit, baud rate settings, deactivation and error handling.
- Monitors and protocol checkers on the interface device side, checking data going in and out of the SCI.
- Support for random and directed test case creation.
- Coverage statistics reporting.
- Log creation for analysis and debug.
For a complete list of features of the SCI Verification IP, visit our website at: http://www.integnology.com
Pricing and Availability
The SCI verification IP will ship in general release to customers on June 1, 2002, supporting both Verilog and VHDL design. The OpenVera SCI verification IP solution comes with full documentation and example configurations for typical interface verification environments. Integnology also offers full methodology training and support services for its products, as well as customized solutions.
OpenVera is an open source hardware verification language developed specifically to meet the unique requirements of functional verification. The language enables users to describe the target application environment, including complex protocols and data objects, at a high level of abstraction, which dramatically increases productivity, readability and reusability. The latest OpenVera developments will be featured at the ninth semiannual Synopsys EDA Interoperability Developers' Forum in Sunnyvale, CA on Tuesday, April 16, 2002. For more information on OpenVera and OpenVera verification IP solutions, visit www.open-vera.com.
About Integnology Corporation
Integnology is a leading provider of product design services. Integnology specializes in ASIC and physical design and verification, as well as FPGA design. Utilizing its expertise in digital, analog, mix-signal design and embedded software development, Integnology has helped customers design systems-on-chip and develop software applications that are crucial for a wide range of products. Integnology's outsourcing services provide faster time-to-market, as well as reduced risk and development cost. Integnology is headquartered in Santa Clara, California. Visit Integnology on the web at http://www.integnology.com.
Synopsys is a registered trademark of Synopsys, Inc. OpenVera and VERA are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.