Shrinks Time-to-Tapeout by Optimizing Verification Efforts
BANGALORE, India, April 15, 2002--Inspiration Technologies Pvt. Ltd., a network chip verification and design consulting company, today announced the immediate availability of two OpenVera™ verification intellectual property (IP) solutions, – CSIX and USB protocols. These verification IP solutions will help designers and verification engineers significantly reduce overall chip development time by reducing the total functional verification time.
"Inspiration Technologies is focused on accelerating product development time for our customers," said Raghavendra Mohan, director of marketing, Inspiration Technologies."We offer a host of verification IP solutions to the fast growing market of OpenVera users, targeted towards networking and communication chip design segments.We provide best-in-class OpenVera verification IP modules to our customers, enabling them to realize higher ROIs and accelerate their time-to-tape out."
To ensure quick ramp-up and maximum re-usability, the verification IP solutions have been built to Synopsys, Inc.'s recommended OpenVera model architecture specifications. Each verification IP includes all interface modules, design examples, a user manual and a quick-start guide, that assists users in stepping through a full-featured reference design making them familiar with the verification IP, in hours.Furthermore, each verification IP from Inspiration has a highly simplified troubleshooting methodology incorporated into it, which coupled with the solid industry experience Inspiration engineers have in ASIC tool use and design services, provides the user community with world-class methodology and technical support.
"The OpenVera verification IP offerings are standards and protocol compliant, ready for plug-and-play use within a complete verification environment consisting of stimulus generators, monitors and coverage objects," said Ravi Shankar, director of ASIC design, Inspiration Technologies."The user can quickly incorporate custom controls and enhance the verification IP to produce their first system level test-suite in a matter of days."
"The objective of OpenVera is to deliver a non-proprietary, open hardware verification language that can help provide solutions to address today's verification-related bottlenecks.The depth of support that OpenVera users can expect is demonstrated by the growing variety and availability of verification IP solutions offered by companies in the Synopsys OpenVera Catalyst Program," said Jim Watts, OpenVera program manager at Synopsys, Inc. (Nasdaq:SNPS) "Catalyst Program members, such as Inspiration Technologies, are trained and supported to apply Synopsys' proven verification technology to complex designs."
Key features of the OpenVera verification IP are:
Common Switch Interface – L1 (CSIX-L1)
CSIX-L1 standards compliant. OpenVera model architecture compliant. User friendly and simple APIs and multiple logging levels for simulation analysis. Fully random or user-controlled traffic injection. Configurable error injection mechanism at frame/transaction levels. User controlled, advanced frame/transaction reporting options.
Universal Serial Bus standards compliant. Synopsys OpenVera model architecture compliant. User friendly and simple APIs and multiple logging levels for simulation analysis. Fully random or user-controlled packet generation and transmission. User controlled, advanced frame/transaction reporting options. Bulk, isochronous, interrupts, control transfers support. IN, OUT, SETUP, PING, split, control setups, device attachments / detachments, Device/hub class requests, suspend/resume control, reset, transaction support. Configurable error injection mechanism at packet/transaction levels. Bus monitor supports packet level, as well as transaction level logging along with protocol error reporting.
Pricing and Availability
The CSIX and USB OpenVera verification IP blocks are now available for either VHDL or Verilog design and verification environments. The verification IP comes with exhaustive documentation including example configurations for typical verification environments. Additionally, Inspiration offers training on the optimal use of Inspiration's verification IP solutions. For current pricing information, please contact firstname.lastname@example.org.
OpenVera is an open source hardware verification language developed specifically to meet the unique requirements of functional verification. The language enables users to describe the target application environment, including complex protocols and data objects, at a high level of abstraction, which dramatically increases productivity, readability and reusability.The latest OpenVera developments will be featured at the ninth semiannual Synopsys EDA Interoperability Developers' Forum in Sunnyvale, CA on Tuesday, April 16, 2002. For more information on OpenVera and OpenVera verification IP solutions, visit www.open-vera.com
About Inspiration Technologies
Inspiration Technologies is a networking chip verification and design consulting company offering a variety of solutions for the global electronic design market ranging from complex state-of-the-art VIPs to offering the best consulting services on full-chip design and system-level verification methodologies and environments. Inspiration also offers consulting on concept-to-silicon/system solutions in the networking domain, to help customers catalyze their time to market goals. Inspiration Technologies is based in Bangalore, India. For further information, please visit http://www.inspiretech.com
Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.