Grenoble, France, May 4th, 2012. Dolphin Integration has selected the Universal Exposition Building of the French Rhône-Alpes region in Shanghai to open their training center which will offer a unique opportunity for local partners to benefit from the transfer of know-how needed for solving SoC and system-level architectural issues.
A long term view
Dolphin Integration SA, which has developed the market for mixed-signal silicon IP in the 90's, soon realized that the future of this market was emerging in China, with Shanghai as the cradle of the Chinese semiconductor industry.
After ten years of IP-only commercial activities for helping a large number of Chinese partners develop optimal and high-performance SoC since early 2002, Dolphin integration figured-out specific needs, improperly served locally, for early performance assessment by simulation prior to any Silicon fabrication.
Indeed, active Chinese innovators cannot benefit locally from the efficient support of Field Application Engineers (FAE) of IP vendors since FAE experts must not be scattered.
In any case, they can only intervene in emergency to fix occasional issues for a given project. Besides users cannot even forecast the impacted performances at system level. Such debugging practices do not guarantee that the same issue will not happen again on future projects and thus postponing again tape-out schedule. Indeed SoC development skills must go far beyond EDA tooling… These considerations have led Dolphin Integration to organize for transferring know-how, beyond FAE's hand-holding, in the form of "Case-study Tutorial Products (CTP)" from their EMBLEM offering.
A three-year strategy had been launched in China by announcing Application Hardware Modeling (AHM) three years ago, for solving design hurdles such as jitter, power supply noise, crosstalk... by which integration and application engineers are faced for high-quality consumer devices aiming at the lowest cost. This three-year strategy was triggered with a demonstration of "AHM approach for Pop-up Noise analysis" in December 2009 at the ICC-CAD in Xiamen, since the first demanding market turned out to be that of high-resolution audio devices.
In December 2010, in Wuxi, Dolphin Integration then unveiled "SuperViCs as the only way to safe SoC Integration", which was followed last November 2011 in Xi'an by a focus on "Minimizing both cost of SoC and risk of bugs at application level with Case-Study Tutorial Products". The ultimate step is now to transfer our know-how through a range of training sessions in China.
Dolphin’s latest product innovations and the associated CTP offering shall be unveiled during the Grand Opening of this training center in Shanghai on Wednesday June 20th, 2012.
It will also be the right time to celebrate the success of the first training session that will be held on June 18 and 19, 2012.
Meanwhile, visitors will also be able to enjoy French cultural events including some French wine tasting, since a pleasurable time is compatible with such a significant innovation!
Registrations are opened only at Dolphin Integration's invitation.
For further information, please contact Nathalie Dufayard at firstname.lastname@example.org
ABOUT DOLPHIN INTEGRATION
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, such as mixed signal high-resolution converters for audio and measurement applications, Libraries of memories and standard cells, Power management networks, Microcontrollers. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Support Engineering with Application Hardware Modeling as well as early Power and Noise assessment, plus engineering assistance for Risk Control.