Jasper Design Automation Releases JasperGold Apps to Solve Tough Challenges and Improve Productivity Throughout the Design and Verification Flow
JasperGold Apps Model Offers Wide Range of Solutions, Flexible Deployment, and Shared Interactive Environment
May 07, 2012 – MOUNTAIN VIEW, CA - Jasper Design Automation, the leading provider of verification solutions based on formal technology, has announced the availability of its JasperGold® Apps products. JasperGold Apps help customers achieve substantial productivity gains in design and verification through individual Apps within a shared interactive environment that fit into existing verification flows. The JasperGold Apps helps solve engineers’ toughest problems, addressing an array of design and verification functionality issues throughout the flow, such as:
- End-to-end property verification,
- Unexpected X detection and debugging,
- Chip-level connectivity,
- Automated assertion generation,
- Identification of coverage holes,
- Design trade-off analysis,
- Absence of deadlock,
- Cache coherency,
- And many more.
For a more detailed list of issues that the JasperGold Apps address, visit http://www.jasper-da.com/products/overview.
JasperGold Apps are built on a single platform that combines multiple formal-based solutions and leverages a common shared database and user interface. The JasperGold Apps architecture enables sharing of design and verification data for each design under test (DUT) between Apps for increased consistency and productivity. The Apps architecture supports deployment of multiple Apps simultaneously as well as multiple invocations of the same App for improved throughput and performance.
The JasperGold Apps architecture is extensible such that customers can take advantage of future Apps that will address emerging design and verification needs. The design and verification challenges that customers have addressed by creating flows using our formal technology have been the inspiration for some of the JasperGold Apps. Customers will be able to continue to leverage the powerful and highly programmable platform in JasperGold to develop their customized flows.
“Customers consistently turn to Jasper for solutions to their complex verification problems, and we are committed to partnering with our customers in support of solving their verification needs,” said Kathryn Kranen, president and CEO of Jasper Design Automation. “The JasperGold Apps model is a critical evolution in verification technology that will make the power of our technology more widely accessible and at the same time make deployment and use more streamlined and efficient.”
“Jasper has created a value-added approach to its formal technology deployment,” said Gary Smith at Gary Smith EDA. “Formal technology has long been thought of as a point tool that addresses only a specific verification issue. Jasper has been able to provide the benefits of their unique formal technology across the entire design and verification flow through easily adoptable apps. This is something the market has needed for quite some time.”
The initial offerings of JasperGold Apps are: the Formal Property Verification App; Connectivity Verification App; X-Propagation Verification App; RTL Development App, Control/Status Register Verification App, and the Architectural Modeling App.
For pricing and sales inquiries about JasperGold Apps, please contact info@jasper-da.com.
About Jasper Design Automation
Jasper Design Automation delivers industry-leading software solutions for semiconductor design, verification, and Intellectual Property (IP) reuse, based on state-of-the-art formal technology. Customers include worldwide leaders in the wireless, consumer, computing, and networking electronics industries. Jasper technology has been an essential part of 150 plus successful chip deployments. Headquartered in Mountain View, California, the company is privately held, with offices and distributors in North America, South America, Europe, Israel, and Asia. Visit www.jasper-da.com to reduce risks, increase design, verification and reuse productivity and accelerate time to market.
|
Related News
- Jasper Releases Two Property Synthesis Apps Targeted at Early RTL Qualification and Coverage-Driven RTL Verification
- Jasper Design Automation Announces JasperGold(R) Verification System v4.5 Featuring Liveness Property Support, Improved Modeling and Faster Engine Performance
- Mentor releases optimized flow, new fill automation for GLOBALFOUNDRIES' 22FDX IC manufacturing process
- Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development
- Cadence to Expand Verification Solution with Acquisition of Jasper Design Automation
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |