Breakthrough technology provides accurate models essential for high-speed system simulations
CAMPBELL, Calif.-- May 14, 2012 -- Sigrity, Inc., the market leader in signal and power integrity solutions, today introduced XcitePI IO Interconnect Model Extraction as part of the company’s comprehensive suite of high-speed analysis software products. This breakthrough technology generates precise chip IO power/ground and signal interconnect models for accurate system-level analysis of high-speed channels and buses. Unique built-in IO quality assessment capabilities enable designers to quickly check IO power/ground robustness and signal electrical performance to identify potential design defects.
Dr. Jiayuan Fang, president of Sigrity, explained that prior to Sigrity’s XcitePI IO Interconnect Model Extraction technology, simultaneous switching output (SSO) analysis was either unduly pessimistic or overly optimistic. The lack of IO interconnect models made the simulated power/ground noise at driver and receiver sides unpredictable, especially when a large number of drivers switch simultaneously. “Accurate models of chip IO interconnects that fully represent the distributed nature of power, ground and signals as well as their electromagnetic coupling effects were not available in commercial EDA flows,” he said. “XcitePI IO Interconnect Model Extraction fills this gap and builds on Sigrity’s capability to provide the accuracy and efficiency needed to model and simulate chip-to-chip signal and power integrity for today’s challenging high-speed designs.”
The chip IO models created by XcitePI IO Interconnect Model Extraction offer both high resolution and compact size to ensure accuracy and efficiency. These models can be used in conjunction with SPICE-compatible circuits for system-level simulations. Taking chip layout data in GDSII or LEF/DEF formats, the XcitePI IO Interconnect Model Extraction tool generates a SPICE netlist that consists of a fully distributed IO power/ground model and IO signal connections from IO cells to bumps. It accounts for all coupling between the power, ground and signals on the chip, the distributed capacitance associated with the power and ground systems, and on-chip decoupling capacitors connected to the power and ground systems. The resulting chip IO interconnect model includes external terminals on the bump side with Sigrity’s Model Connection Protocol (MCP) header information for easy connection to IC package models. Similarly, the model includes external terminals at the IO cell level to streamline connection with targeted driver/receiver models. Thus XcitePI IO Interconnect Model Extraction provides precise interconnect models for chips, packages and boards – an essential requirement for accurate signal integrity analysis of high-speed channels and buses.
The Sigrity XcitePI IO Interconnect Model Extraction tool also enables quick assessment of power and ground quality along with signal performance at every IO cell. Graphical representations of electrical performance at each cell help users quickly identify weak or problematic physical areas and perform what-if analysis to rapidly improve the design.
Sigrity’s product line includes a full complement of robust extraction tools and a comprehensive simulation environment for high-speed analysis. Sigrity’s XtractIM is used for IC package model creation and assessment. For board level models, Sigrity’s PowerSI is used to create board and/or package s-parameter models that are converted into SPICE-compatible circuits by Broadband SPICE. Sigrity’s SystemSI product family provides a comprehensive environment for evaluating entire chip-to-chip channels with customizations targeting parallel and serial bus applications. It offers a way to jump-start DDR and SerDes projects with very early reliability assessment and add more detailed models as design refinement progresses.
XcitePI IO Interconnect Model Extraction is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement. XcitePI applications enable both transient and frequency domain simulations of the full-chip power delivery network and take IC package effects into account; they also facilitate chip-level what-if analysis to evaluate decoupling capacitor placement along with the impact of power grid and bump design changes. A unique XcitePI planning module enables chip-level studies to begin early.
Pricing and Availability
XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms with pricing starting at $108,000 for a 3-year license.
Sigrity, Inc., a privately held U.S. company incorporated in 1998, delivers advanced software solutions for package physical design and for analyzing power and signal integrity in chips, packages and printed circuit boards. Sigrity’s patented electrical analysis methodologies run orders of magnitude faster than general purpose electromagnetic tools, helping leading companies in the semiconductor, computer, graphics, communications and networking industries ensure high performance and reduce time to market. The company is headquartered in Campbell, California with direct sales and global distribution through worldwide representatives. For more information please visit: http://www.sigrity.com.