Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
Complete IP Subsystem Enables Fast Development of SoCs at Lower Cost
SAN JOSE, Calif. -- 15 May 2012 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today launched the industry’s first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem is the industry’s first to feature fully-integrated component IP, including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog. This high level of integration enables easy implementation of NVM Express in SoC designs.
NVM Express is a specification that will speed the broader adoption of PCI Express-based SSDs by improving performance and reducing power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCI Express implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCI Express-based SSDs.
“Our studies find that PCI Express is poised to become the preferred embodiment of NAND in the enterprise, and this will lead to expanding adoption of the NVM Express protocol,” said Jim Handy, director, Objective Analysis. “Today several vendors produce PCI Express SSDs based on an SSD array architecture, but over time we expect these to yield to faster designs that remove the intervening step and allow NAND flash to communicate directly using an NVM Express interface, as supported by the Cadence suite.”
“Cadence combined our expertise in interface IP, analog/mixed signal technologies, and system verification to offer customers a complete and full-featured NVM Express interface subsystem,” said Martin Lund, senior vice president, Research and Development, SoC Realization Group, Cadence. “Without this subsystem approach, SoC designers would need to source their interface component IP separately and drive integration on their own, often increasing their design risk and overall development time for new SoCs.”
The controller used in the Cadence NVM Express solution supports advanced command management, data tiering and hardware command acceleration. The IP is highly configurable, allowing it to target the broad scope of applications possible with NVM Express. The included driver firmware offers an easy interface to the system firmware. The solution also includes a verification and test environment spanning from the PCI Express interface to the internal bus fabric.
Cadence offers a design methodology that uses the Cadence Virtual System Platform, NVM Express and PCI Express verifications models, Cadence Incisive® Software extensions and flash memory models to accelerate the design and integration of the Cadence NVM Express IP solution. These components provide a scalable verification and test platform for system-level software and hardware development and testing.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- Mobiveil Announces the Availability of All Key IP Components and Subsystem for an Integrated NVM Express Based PCIe-SSD Solution
- NVM Express Releases NVM Express Specifications to Unify AI, Cloud, Client, and Enterprise Storage
- NVM Express Announces the Release of the Computational Storage Feature
- Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
- Solid State System Co., Ltd. selects Andes AndesCore N9 for Its SSS6131 USB 3.1 Gen 1 Flash Controller Highly Demand for Storage Application
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |