ANDOVER, Mass., May 29, 2012 -- Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its NVM-Xactor verification IP targeting Non-Volatile Memory Express (NVMe) for high performance PCIe-based SSDs. NVM-Xactor extends Avery's portfolio of storage-related VIP which also includes USB Attached SCSI (UASP), USB Mass Storage Class Bulk-Only Transport (BOT), MIPI Universal Flash Storage (UFS), and SATA.
NVM-Xactor is a complete verification solution for NVMe core and system design. NVM-Xactor allows design and verification engineers to quickly and extensively test the functionality of NVMe controller-based designs. The NVM-Xactor solution includes:
NVM-Xactor works in conjunction with Avery's leading PCI-Xactor PCI Express Verification IP solution to supply a complete NVMe subsystem verification environment. A NVM bus adaptor layer provides a virtual task interface to the NVM host software BFM to hook up to any bus interface such as PCIe and AMBA AXI which enables running the NVM host software BFM with or without the PCIe root complex and endpoint stacks yielding faster simulation performance for large data movement and supports both NVMe core-level and SOC-level verification environments. A reference NVMe controller layer also supports core-level verification by emulating the NAND Flash backend subsystem.
Models and compliance testsuites are developed in SystemVerilog and support UVM, OVM, and VMM environments.
"Avery is focused on delivering industry leading VIP for the rapidly emerging storage-related standards built on top of PCIe, USB, and MIPI base protocols", says Chilai Huang, president of Avery Design Systems. "Our solution enables designers to thoroughly verify their designs functionally adhere to the new NVM Express standard and effectively pinpoint areas of non-compliance or performance bottlenecks."
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, X verification, and RT-level DFT at-speed testability analysis; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, MIPI, DDR/LPDDR, and NVM Express standards; and scalable distributed parallel logic simulation. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com .