49th Design Automation Conference – San Francisco, California, June 5, 2012. Target Compiler Technologies, the leader in ASIP design tools, today announced the commercial release of a new graphical debugger tool for multicore system-on-chip architectures. The new multicore debugger, named ChessMP™, seamlessly integrates with Target’s instruction-set simulation technology for processor cores, thus enabling cycle and instruction-accurate simulation of multicore architectures. Additionally, ChessMP easily connects to FPGA and ASIC implementations of the multicore system through a JTAG-based communication API, thus enabling multicore on-chip debugging.
Today’s release of the ChessMP multicore debugger marks the first phase in the commercial release schedule of Target’s new MP Designer™ product line. MP Designer is a new tool-suite for the design and programming of multicore SoC architectures unveiled last year. In addition to the multicore debugging capabilities released commercially today, MP Designer will support key design tasks such as the parallelization of sequential C code for multiple cores and the generation of a communication fabric between such cores. Those functionalities are currently available for beta testing to selected customers, and their commercial release is slated for the end of 2012.
ChessMP's graphical user interface (click for full-resolution image)
ChessMP offers software developers complete visibility and control of all processor cores in a multicore architecture. For each core, ChessMP’s graphical user-interface displays the software program in C source and assembly code, the memory and register status, source code variables, the processor pipeline, and a multitude of debugging and profiling views. The user-interface can be reconfigured dynamically through mouse drag-and-drop actions, so that at each time instance during the debug cycle only the relevant cores are visible. This way, debugging of a large number of cores becomes practical within the available computer screen real estate. In addition, ChessMP supports both synchronous and asynchronous stepping and execution of code, local and global breakpoints on C and assembly code, and local and global watchpoints on register and memory locations.
Although part of Target’s new MP Designer product line, Target also offers the ChessMP multicore debugger as a separate add-on module to users of IP Designer™, Target’s flagship EDA product for the design and programming of application-specific processors (ASIPs). Several IP Designer customers already incorporated the new multicore debugger in their design flow.
“The commercial release of our new multicore debugger is an important milestone in our product expansion strategy, which aims at extending the reach of our EDA tools from the level of IP cores towards Iarger IP subsystems,” says Dirk Lanneer, VP Tool Development at Target. “IP Designer, our legacy tool-suite for ASIP design, is being adopted by a growing number of semiconductor and system companies. Many of these customers are designing multicore systems. Our upcoming MP Designer tool-suite, including the new multicore debugging capabilities announced today, will bring the design of multicore SoCs within easy reach of our current and future customers,” Lanneer adds.
This announcement marks one of several announcements made today by Target.
About Target Compiler Technologies
Target Compiler Technologies (www.retarget.com) is the leading provider of retargetable software tools to accelerate the design, programming and verification of application-specific processor cores (ASIPs). Target's IP Designer tool suite is ideally suited for SoC designs in markets that mandate low silicon cost, low energy consumption, and flexibility to accommodate algorithmic changes. The tools have been used by customers around the globe to design SoCs for 2G/3G/4G handsets, cordless and VoIP phones, audio/video/image processing, infotainment and security for cars, DSL modems, DSL access multiplexers, wireless LAN, hearing instruments, and personal healthcare systems. Target is a spin-off of the Belgian nano-electronics R&D center IMEC, is headquartered in Leuven, Belgium, with North American operations in Boulder, Colorado.