LONDON In a development that could boost channel coding efficiency of wireless communication standards, researchers at the Interuniversities Microelectronics Center (Leuven, Belgium) say they have implemented a convolutional turbo coding core capable of performing encoding and decoding functions faster and with less power than available methods.
IMEC's Turbo coding at Minimum Power (Tampo) intellectual property core can provide encoding and decoding for forward error correction at data rates up to 100 Mbits/second. This can be accomplished with latencies of less than 10 microseconds and energy of less than 50-nanojoules per bit, according to Liesbet van der Perre, wireless program manager at IMEC.
Prior to the development of the Tampo core architecture, convolutional turbo codes had been limited to data rates of about 2 Mbits/s, said van der Perre. An alternative form of turbo coding, known as block codin g or turbo product codes (TPCs), is capable of data rates in excess of 100 Mbits/s, but "block codes have problems with power and latency," van der Perre said.
The Tampo core is currently running in simulation to prove out the architectural optimizations made by van der Perre's group. The core occupies 400,000 gates, includes 36 kbytes of SRAM and achieves its 100-Mbit/s throughput from a 200-MHz clock frequency. The core has been taped out to a 0.18-micron CMOS ASIC design flow and working silicon is due to become available in the second quarter of 2002.
Until then, IMEC is prepared to make Tampo available as a documented design database comprised of high-level descriptions written in C++ and C, down to VHDL circuit descriptions. Licenses start at $200,000 for the full duplex version.
"There was a big problem to implement turbo coding at high-speed, but also at low power and lower latency," said van der Perre. The group set itself a latency limit of 10 microseconds, a figure it felt was reason able enough to support interactive communications.
The result is a 3-dB to 5-dB efficiency gain over Viterbi decoding. In wireless applications this can be turned into 50-to-70 percent transmit power saving, or a bandwidth saving of 20-to-30 percent, or an increase in range for a given power level of 25-to-50 percent, van der Perre said. Bit error rates of 10-7 are achieved at signal-to-noise ratios of 4 dB. The team estimates the decoding energy to be less than 50 nanojoules per bit, which they call a world record.
The turbo codes could be applied to existing and to future wireless communications standards to improve their channel coding efficiency, van der Perre said. The codes could be retrofitted to established wireless LAN standards such as 802.11a and HiperLAN 2 to improve the energy efficiency of transmission, and they will certainly be considered for 4G standards, he said.
Product or convolution coding
Advanced Hardware Architectures Inc., an established supplier of turbo-code codecs in silicon, has developed a product code version of turbo code technology.
"We have turbo [product] code silicon running at 155-Mbit/second and we're looking at much faster devices to come," said Keith Pickavance, a principal research engineer with AHA based in Southampton, England.
Pickavance said the latency of TPCs depends on the block size. A 4-kbit block size would result in a delay of about 50 microseconds in current implementations, but smaller delays would be obtained if larger block sizes were selected, he said.
Pickavance rejected IMEC's contention that TPC has a problem with power efficiency.