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Cap-less 106 dB dynamic range ADC with low power mode and ultra-low latency capability
Xylon announces logiI2C Master Controller IP core for Xilinx FPGAs
New I2C Bus Master Controller IP core
July 9, 2012, Zagreb (Croatia) – New logiI2C Bus Master Controller IP core from Xylon's logicBRICKS IP library supports single master I2C communications and enables bug-free data transfers. It is ARM® AMBA® AXI4-Lite bus compliant, and can be implemented in all Xilinx programmable devices, including the 7 series FPGA families and the Zynq™-7000 EPP.
Xylon delivers the logiI2C IP core in a format which is fully compatible with Xilinx Platform Studio (XPS), and the software driver compatible for use within Xilinx Software Development Kit (SDK).
The logiI2C IP core license fees offered through Xylon's Low-Volume IP Program (LVIP) start at €850 (< $1,050).
For datasheet and general information about the logiI2C I2C Bus Master Controller IP core please visit:
http://www.logicbricks.com/Products/logiI2C.aspx.
The logiSDHC can be evaluated on Xylon's logiCRAFT-CC Companion Chip Kits, or third-party hardware platforms.
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