Peter Clarke, EETimes
7/27/2012 4:17 AM EDT
LONDON – Fully depleted FinFET style transistors made on SOI wafers are likely to allow between half and one-third the leakage current of FinFETs made on bulk silicon according to TCAD simulations performed by Gold Standard Simulations Ltd. (Glasgow, Scotland).
Professor Asen Asenov, CEO of GSS, has written a series of blogs on the company's website discussing simulations of FinFETs that use the company's simulation tools. A starting point was shape of Intel's FinFETs in a 22-nm bulk silicon process. The simulations are performed using the company's Garand statistical 3-D TCAD simulator. He came to the conclusion that Intel may find it necessary to move to FinFET-on-SOI to shrink its process below 22-nm and that foundries yet to introduce FinFET processes would be advised to pay attention.
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