Bytom -- August 23, 2012 -- Digital Core Design, IP Core provider and SoC design house introduced the newest version of DoCD. It is a complete debugging system, which consist of three main blocks: Debug IP Core, Hardware Assisted Debugger (HAD2) and Debugging Software. DoCD v.6.01 offers real time, non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on chip software debugging. As an effect, prominently cuts debugging time.
Modern System-on-Chip designs are facing the problem of inaccessibility of important control and bus signals. They often lay behind the physical pins of the device and that is why traditional measurement instrumentation is useless in many cases. The best way to get around those limitations, is to use on-chip debug tools for the tasks verification and software debugging. – DoCD allows hardware breakpoints, trace, variables watch and multi C sources debugging – explains Jacek Hanke, DCD’s CEO – Moreover, our Debug Software can work both as a hardware debugger and a software simulator. Some tasks can be validated at software simulation level and after this step, you can continue real-time debugging, by uploading code into silicon.
Other advantage of an on-chip debugger, is its improved design productivity in an integrated environment, with graphical user's interface. Thanks to it, DoCD offers ability to display/modify memories' content, processor's and peripherals' register windows, along with information tracing and ability to see the related C/ASM source code. And as a final result, these are the key elements, that help to improve the design process and thereby, to increase productivity.
Complete DoCD system consists of three major parts:
- Hardware Assisted Debugger: Pendrive packaged - HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (JTAG protocol) inside silicon and a USB port of the host PC, running DoCD Debug Software.
- Debug Software: is a Windows based application, compatible with all existing compilers and assemblers. The DS was designed to work in two major modes: software simulator and hardware debugger mode. They allow pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon - using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions or stopped at any of the breakpoints.
- Debug IP Core: is a real-time hardware debugger, which provides an access to all chip registers, memories and peripherals, connected to the IP Core. It controls CPU work, by non-intrusive method. The Debug IP Core is provided as VHDL or Verilog source code, as well as CPLD/FPGA EDIF netlist.
The DoCD provides a scaled solution - many SoC designs have both power and area limitations. Debug IP Core, can be scaled to control gate count. The benefit is fewer gates - for lower use of power and core size, while maintaining excellent debug abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation), with less features availed in the final silicon.
Tab. 1 DCD’s on Chip Debugger area utilization.
About Digital Core Design:
Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and since the early beginning has been considered an expert in IP Core architecture improvements. Thousands of customers became convinced by our unique solutions and billions of people worldwide use our technology in USBs, MP3 players, mobile phones and many other applications.
The innovativeness of DCD's IP solutions has been confirmed by over 500 licenses sold to over 300 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, OSRAM, GENERAL ELECTRIC, SILICON GRAPHICS, RAFAEL, SAGEM or GOODRICH.
More information: http://dcd.pl/page/147/about/