SAN JOSE -- During the Embedded Processor Forum here next week, Micron Technology Inc. is expected to take a step into the general-purpose, embedded microprocessor market, announcing a system-on-a-chip (SoC) technology for use in a range of applications.
Micron's embedded processor, dubbed "G0," is based on a RISC processor architecture from Mips Technologies Inc. Last year, Micron licensed the 32- and 64-bit RISC cores from Mips Technologies of Mountain View, Calif.
"G0" not only consists of a RISC engine, but it also makes use of the company's embedded DRAM technology as well. The product also consists of I/O, a crossbar switch, and other logic on the same device.
"This is an SoC," said Dean Klein, vice president of market development for Boise-based memory giant Micron. "This technology is an SOC with embedded DRAM," Klein said.
Micron has produced "G0" in the fab, but it has not commercialized the product--yet, he said. Right now, "G0" is a technology demonstration to prove the company's SoC and embedded DRAM design capabilities, he said. "It's a technology vehicle," he told SBN today.
But the Micron executive dropped hints that the company may develop standard and custom parts for the commercial market. If or when the company brings this technology into the marketplace, the product will be geared for a wide range of applications.
"It can be used as a network management plane processor," he said. "It's a good fit for office equipment. It is also aimed for PDAs, cellular phones, and cable modems."
The product combines a RISC engine with the company's own embedded DRAM and memory technologies. Based on a 0.18-micron process, "G0" is built around Mips Technologies' 166-MHz MIPS 4Kc processor core. The processor core itself is called the SC1, which can be developed in the form of a standard product or a re-usable intellectual-property (IP) core.
The device also integrates 1-megabyte of embedded DRAM components, whi ch are organized in a 64-kilobit x 128 fashion. In total, the "G0" platform consists of eight 1-Mbyte embedded DRAM components, for a total of 8-Mbytes of DRAM on the device itself.
The "G0" also makes use of a non-blocking crossbar switch, which has a total bandwidth of 6-gigabits-per-second. It also consists of I/O, including UARTs, four Universal Serial Bus (USB) ports, dual ATA ports, and an AC'97 codec.
Micron will disclose more details at the Embedded Processor Forum, which takes place from April 29 to May 2 in San Jose.