Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys
Chris Edwards, New Electronics
September 11, 2012
Some 15 years ago, Synopsys bet on the idea that third party intellectual property (IP) would an important element of the integrated circuit business. Interviewed towards the end of the 1990s, Synopsys' cofounder Aart de Geus – now its co ceo – talked about the problems that chip designers faced as the gap between what Moore's Law could deliver and the number of transistors in a circuit they could realistically deploy per day grew larger. In that interview, de Geus said: "I am totally convinced that reuse is necessary to the advancement of silicon."
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation