Toshiba develops configurable processor core
Toshiba develops configurable processor core
By Yoshiko Hara, EE Times
April 29, 2002 (8:35 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020429S0047
TOKYO Toshiba Corp. will take the wraps off a configurable processor core that can be customized according to application at the Embedded Processor Forum this week in San Jose, Calif. The company plans to promote the MeP for "media embedded processor" as a de facto standard embedded solution for multimedia use.
Toshiba will offer MeP in two forms: as a family of system-on-chip ICs; and as licensable intellectual property (IP). A low-power version is scheduled to hit the market this year. For IP sales, Toshiba said it might recruit third parties to prepare a design environment.
Based on Toshiba's original 32-bit RISC architecture, the MeP core uses 16- and 32-bit variable-length instructions, and has 16 general-purpose registers, as well as a five-stage pipeline.
Depending on the application requirements, the core can be configured using varying instructions, memory configurations, debug support, interrup t controller, timer/counter and bus interface width.
'MeP modules'
Extensions in the form of hardware and software IP can be added to form "MeP modules." Extensions include user custom instructions, a DSP unit, hardware engines and a very long instruction word coprocessor. MeP modules with different functionality, such as video and audio decoders, are linked to a global data bus to form a one-chip system.
Toshiba started MeP architecture work around 2000 and developed an MPEG-2 high-definition decoder last year. Now the MeP engineers are working on a low-power version, called c2, using a 0.13-micron process. MeP-c2's minimum configuration has 46,000 gates, operates at 200 MHz (worst case), and packs a 2-kbyte Level 1 cache and 16 kbytes of data RAM.
Power consumption is 0.11 milliwatt per megahertz, which Toshiba said is about one-third the average power consumption of several 32-bit processors with the same size memory.
More Embedded Processor Forum coverage.
Related News
- Toshiba Develops DNN Hardware IP for Image Recognition AI Processor Visconti 5 for Automotive Driver Assistance Systems
- ARC and Toshiba Extend Collaboration to Develop Next Generation Multicore Configurable Processor Technology
- Toshiba and ARC Collaborate to Grow Industry Adoption of Configurable Processor Technology Worldwide
- Toshiba Selects Cadence Tensilica Vision P6 DSP as Image Recognition Processor for its Next-Generation ADAS Chip
- NSITEXE Develops Test Chip with Next-generation Semiconductor IP Core Called a DFP
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |