Digital Blocks showcases its UDP/IP Off-Load Engine at the HPC Wall Street Conference on September 19th, Roosevelt Hotel, 70 Vanderbilt Ave, New York, NY 10017
New York, Sept 21, 2012 – Digital Blocks, a leading developer of ultra-low latency networking IP Cores for FPGA accelerated Financial Applications on High-Frequency Trading Systems, today announces the DB-UDP-IP-HFT IP Core, a UDP/IP Hardware Stack / UDP Off-Load Engine (UOE) targeting Altera Stratix V and Xilinx Virtex 7 FPGAs on leading-edge network adapter cards with one or more 10 / 40 GbE network links.
Digital Blocks’ UDP/IP Off-Load Engine (UOE) targets trading systems with sub 100 nanosecond requirements. Along with FPGA design services, Digital Blocks works with Financial Trading companies in architecture & design of proprietary trading systems. Please go to Digital Blocks HFT page for more information www.digitalblocks.com/High-Frequency-Trading-IP-Cores-And-Systems.html
Price and Availability
The DB-UDP-IP-HFT IP Core is available immediately in synthesizable Verilog, along with a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with High-Frequency Trading Networking, Embedded Processor & Peripherals, Display Controller, Display Link Layer, 2D Graphics, and Audio / Video processing requirements.
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; eFax: +1-702-552-1905; Media Contact: firstname.lastname@example.org; Sales Inquiries: email@example.com; On the Web at www.digitalblocks.com.