Technology Trends: DDR4 first look
Kristin Lewotsky, EETimes
9/27/2012 2:26 PM EDT
Some seven years after launching development of DDR4, JEDEC has officially released the new standard (JESD79-4). DDR4 features a per-pin data rate of 1.6 GT/s, with an initial maximum objective of 3.2 GT/s. With DDR3 exceeding its original targeted performance of 1.6 GT/s, look for higher performance speed grades to be added in future releases. The DDR4 architecture consists of an 8n prefetch with two or four selectable bank groups, which enables simultaneous activation, read, write, or refresh operations to be conducted in each unique bank group. The standard was also designed to encompass stacked memory, with stacks of up to eight memory devices acting as a single signal load. With the announcement, we thought it was a good opportunity to sit down with Todd Farrell, chairman of the JC-42.3C Subcommittee for DRAM Timing and director of technical marketing at Micron, to learn more.
E-mail This Article | Printer-Friendly Page |
|
Related News
- Implement seamless DRAM processing speeds utilizing Silicon Proven DDR4/LPDDR4/DDR3L Combo PHY IP Core in 12FFC process technology
- DDR5/DDR4/LPDDR5 Combo PHY IP Cores which is Silicon Proven in 12FFC with Matching Controller IP Cores is available for license to accelerate your Memory Interfacing Speeds
- A closer look at TSMC's 3-nm node and FinFlex technology
- Experience DDR5/DDR4/LPDDR5 Combo PHY and matching Controller IP Cores seamless RAM interfacing speeds, with Silicon Proven 12FFC technology
- Introducing DDR5/DDR4/LPDDR5 Combo PHY IP Core, Silicon Proven in 12FFC for Next-Gen High performance SoCs is available for immediate licensing
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024