Addressing IP and SoC Verification, New Incisive Debug Analyzer Reduces Average Debug Time Up to 40%
SAN JOSE, Calif., 09 Oct 2012 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced the Incisive® Debug Analyzer, a new and innovative verification debug product for RTL, testbench and SoC verification that offers significant reductions in debug time and effort. Cadence® customers who have used this unique, multi-language debug solution have reported average time savings of up to 40 percent or more.
“Incisive Debug Analyzer is an innovative debug technology that has helped us fix bugs in minutes that previously would have taken hours to debug, including the root cause of complex multithreaded behaviors in our HDL design and, more importantly, in the verification environment,” said Eli Zyss, vice president of Silicon Design at Altair Semiconductor. “We see many verification and design engineers leveraging the post-process playback debugger and the cause analysis capabilities in Incisive Debug Analyzer. It is a great debug productivity enhancer.”
With many SoC companies now spending over 50 percent of their overall verification effort in debug, Incisive Debug Analyzer targets this significant verification bottleneck with unique debug features. For instance, the debugger allows users to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL). Additionally, users can click directly on a line or variable to jump forward or backward through time to the point when the source code line was executed or a variable value changed, allowing them to pinpoint the bug(s).
Other unique features include integrated, interactive log file analysis capabilities with smart filtering and clickable messages that take users directly to the point of interest in either the source code or the waveform database. The debugger provides relevant debug investigation information that allows users to quickly and easily filter messages coming from any platform (HVL and HDL code) and explore the cause of the messages by providing causality relations and debugging leads.
“Our customers have been seeking a comprehensive RTL, testbench and SoC debug solution to cut through the bottleneck of verification debug,” said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence. “Incisive Debug Analyzer provides them with the capabilities, accuracy, flexibility and speed to isolate and fix their bugs in record time.”
The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. It is scheduled for release by year’s end.
Cadence is hosting a webinar Oct. 10 to give customers a sneak peek at the new debugger. Visit the Cadence Web site for additional information.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.