Hsinchu, Taiwan, R.O.C. – October 12, 2012 – TSMC (TWSE: 2330, NYSE: TSM) today announced that it has taped out the foundry segment’s first CoWoS™ (Chip on Wafer on Substrate) test vehicle using JEDEC Solid State Technology Association’s Wide I/O mobile DRAM interface. The milestone demonstrates the industry’s system integration trend to achieve increased bandwidth, higher performance and superior energy efficiency.
This new generation of TSMC’s CoWoS™ test vehicles added a silicon proof point demonstrating the integration of a logic SoC chip and DRAM into a single module using the Wide I/O interface. TSMC’s CoWoS™ technology provides the front-end manufacturing through chip on wafer bonding process before forming the final component. Along with Wide I/O mobile DRAM, the integrated chips provide optimized system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth.
A key to this success is TSMC’s close relationship with its ecosystem partners to provide the right features and speed time-to-market. Partners include: Wide I/O DRAM from SK Hynix; Wide I/O mobile DRAM IP from Cadence Design Systems; and EDA tools from Cadence and Mentor Graphics.
“Silicon validation is a critical step in the development of a highly advanced and complete CoWoS™ design solution,” said Cliff Hou, Vice President of Research and Development at TSMC. “The successful demonstration of the JEDEC Wide I/O mobile DRAM interface highlights the significant progress TSMC and its ecosystem partners have made to capitalize on the performance, energy efficiency and form factor advantages of CoWoS™ technology.”
“Collaboration with TSMC will enable SK Hynix to satisfy customer demand in system integration and we expect to implement JEDEC compatible integration products in advance,” said Sungjoo Hong, Senior Vice President and Head of R&D Division of SK Hynix.
“TSMC and Cadence have worked together to validate the industry’s first design IP for Wide I/O in TSMC’s CoWoS™ process,” said Martin Lund, Senior VP of Silicon Realization Group at Cadence. “Our design IP is capable of over 100Gbit/sec of DRAM bandwidth at very low power when connected to Wide I/O devices meeting the JEDEC JESD229 Standard. The test and characterization abilities of Cadence’s design IP and TSMC’s CoWoS™ process provide TSMC’s customers a reliable path to success with Wide I/O.”
“Mentor Graphics and TSMC continue collaborating to make sure mutual customers can use ever expanding 3DIC design techniques that are silicon proven,” said Joseph Sawicki, vice president and general manager of the design to silicon division at Mentor Graphics. “Mentor and TSMC have developed a design flow that creates minimal disruption to existing flows, while still providing the highest value for our mutual customers.”
CoWoS™ is an integrated process technology that attaches device silicon chips to a wafer through chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. TSMC CoWoS™ technology has entered the pilot production stage.
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s managed capacity in 2011 totaled 13.22 million (8-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB™ facilities, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China, and its joint venture fab, SSMC. TSMC is the first foundry to provide 28nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.