BALTIMORE--At the International Test Conference here today, Synopsys Inc. announced new advanced test modeling technology that will more than triple the capacity of the company's design-for-test complier software, while increasing the tool's speed by seven times without impacting IC-layout optimization features.
The Mountain View, Calif.-based company also announced a new option to its automatic test pattern generation products, called TeraMax ATPG, which enables designers to detect timing-related defects during manufacturing test. The enhancements are aimed at enabling test technology to keep up with the growing complexity of IC designs.
According to Synopsys, up to half of manufacturing defects in today's IC designs are timing related, and these problems may not be caught without specifically targeting delay defects. Synopsys said its TetraMAX DelayTest is a structured, scan-based approach to delay testing that's compatible with low-cost automatic test equipment.
"Achieving fully testable semiconductor devices today requires that DFT [design-for-test] products stay ahead of the design complexity curve," said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Business Unit. He said Synopsys has included a new breakthrough test modeling technology into its DFT complier to handle complex multi-million gate system-on-chip designs.
"This new test modeling technology is based on the proposed IEEE P1450.6 Core Test Language (CTL) standard," Domic said.
The new capability in Synopsys' DFT compiler will be available in December. Current customers using the DFT compiler will receive this new capability at no additional charge as a maintenance update, the company said. Pricing for the new compiler begins at $22,500 for a one-year technology subscription license.
The DelayTest option to TetraMAX ATPG is now available with prices beginning at $36,660 for a one-year subscription license.