Awards Acknowledge Key Contributions to 3D-IC CoWoS Technology
SAN JOSE, Calif., 29 Oct 2012 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, was presented two “Partner of the Year” awards from TSMC for the contributions Cadence engineers made in the emerging areas of 3D-IC and 20-nanometer chip development. The awards--for “CoWoS Design Enablement and Test Vehicle Development” and “Joint Delivery of the 20-Nanometer Reference Flow”—recognize the expertise, technology leadership and commitment Cadence brought to the table as it has worked tightly with its long-standing foundry partner to enable advanced chip design and manufacture.
Martin Lund, senior vice president of R&D for the SoC Realization Group at Cadence (right), and Dr. Cliff Hou, vice president, Research & Development, TSMC
“TSMC’s partner awards are testament to the power of collaboration,” said Chi-ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “By working so closely together and for so many years, we are able to offer our customers an easier path past the most daunting challenges they face in the key areas of 3D-IC and 20-nanometer design. Whereas we proudly accept these awards, the real winners are our customers.”
Dr. Chi-Ping Hsu, senior vice president of R&D for the Silicon Realization Group at Cadence (right), and Dr. Cliff Hou, vice president, Research & Development, TSMC
“These awards recognize the engineering contribution from Cadence that has enabled 3D-IC and 20-nanometer design,” said Suk Lee, TSMC senior director of the Design Infrastructure Marketing Division of TSMC. “Cadence continues to provide advanced technology and collaborates closely with TSMC to enable significant advances in semiconductor and system design.”
TSMC recently selected Cadence® solutions for its 20-nanometer design infrastructure. The solutions include the Virtuoso® custom/analog and Encounter® RTL-to-signoff platforms. TSMC also validated Cadence 3D-IC technology for its CoWoS (chip-on-wafer-on-substrate) Reference Flow; the companies developed a CoWoS test vehicle that includes Cadence Wide I/O memory controller and PHY IP.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.