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Huawei, Altera mix FPGA, memory in 2.5-D device
Rick Merritt, EETimes
11/14/2012 6:59 PM EST
SANTA CLARA, Calif. – Huawei and Altera will package an FPGA and a Wide I/O memory on a 2.5-D silicon interposer to bust through memory bandwidth limits in communications systems. The technology presents thorny challenges but could become critical in networking, said a senior scientist for Huawei.
The new device, in the works only about three months, will significantly reduce board space while increasing performance. “2.5D silicon interposers seem to be the best fit for networking companies—in fact, they are mission critical,” said Anwar A. Mohammed, a senior staff scientist for packaging working in Huawei’s U.S. R&D center here.
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