San Jose, CA - MIPS Technologies recently enhanced its MIPS32 and MIPS64 RISC microprocessor architectures.
Among other changes, MIPS tried to reduce the architecture's interrupt latency by implementing general purpose register (GPR) shadow sets, which eliminate the need to save and restore GPRs when servicing an exception or interrupt. This reduces register save time to the duration of a pipeline flush.
In addition, the architectures were endowed with vectored interrupts, which can save up to 20 cycles, thereby decreasing interrupt latency.
MIPS also enabled the architectures to manipulate bits within data packets and device registers.
The enhanced architectures allow MIPS64-compliant coprocessors, such as floating processor units (FPUs), to be combined with a 32-bit CPU.
The architectures' MMUs are capable of managing pages as small as 1KB or as large as 256MB. The support for small page sizes is useful in memory-constrained ap plications. Large page support allows regions of virtual memory to be mapped with a single transition look-aside buffer entry allowing, for example, network applications to map and protect a memory-resident database.
The enhanced architectures will support all legacy IP and will be compatible with third-party tools, operating systems, and application software supporting the MIPS architecture.
The MIPS32 and MIPS64 architectures with the enhancement described above are available for licensing now.