HyperTransport layers on extensions for comms equipment
HyperTransport layers on extensions for comms equipment
By Rick Merritt, EE Times
May 9, 2002 (12:38 p.m. EST)
SAN MATEO, Calif. The HyperTransport consortium has announced extensions to its specification geared at pushing the gigabit interconnect beyond its PCI heritage and making it more suitable for use in communications systems. The work is one of several enhancements in the pipeline that also include a speed boost from 1.6 to better than 3 Gbits/second, a coherency spec for multiprocessing and a compliance testing program.
Separately, talks between developers of the competing RapidIO and PCI Express interconnects seeking to harmonize those efforts have broken down.
Both HyperTransport, initially developed by Advanced Micro Devices Inc., and PCI Express (formerly called 3GIO), led by Intel Corp., are seeking to reach beyond some of their legacy constructs from the PCI bus as they seek design wins in routers, switches and other communications gear. RapidIO, led by Motorola Inc., was aimed at comms systems from the outset, making a cle an break with the address-based semantics and tree topology of the Peripheral Component Interconnect local bus.
The HyperTransport extensions add a layer to the spec that covers a message-passing interface for handling packet data and streaming packets to an address. The extensions also support direct peer-to-peer transactions between line cards without going through or reflecting data at a host processor, as would have been required under PCI's tree structure.
In addition, the spec will now support 16 streaming point-to-point channels in hardware, a feature expected to make it easier to bridge between HyperTransport and the Systems Packet Interface (SPI) 4.2 interface typically used in communications data plane chips such as framers or Ethernet aggregation devices. The extensions also add an optional capability to extend addressing from 40 to 64 bits and error-handling features that will be needed as HyperTransport hits faster data rates.
The comms extensions will fortify the competitive position of HyperTransport in a growing universe of fast interconnect technologies. But the additions are not expected to persuade the members of competing camps to join HyperTransport, said Nathan Brookwood, analyst with Insight64 (Saratoga, Calif.).
The goal of the work was to extend HyperTransport to cover all three key comms chip link points the control plane, data plane and lookaside interface, said Brian Holden, principal engineer of PMC-Sierra's MIPS division and chair of the HyperTransport task force that defined the extensions. "We wanted one interface to fit all three places to reduce system complexity," Holden said.
HyperTransport already lost an initial vote by the influential Network Processor Forum, which picked SPI 5 for a high-speed lookaside interface. The forum recently formed an ad hoc group to investigate whether it should also set a standard for a control plane interface.
Backers said the HyperTransport extensions will let the interconnect flexibly handle both comms-like tasks and topologies for network processors and line cards, and such PCI-like jobs as exception and configuration management for host controllers. "There is some overhead for legacy PCI traffic, but it seems like it is very moderate [compared with the wealth of PCI chips and boards available to leverage]," Holden said.
"The software compatibility [with PCI] is pretty important," said Jim Keller, chief architect of Broadcom Corp.'s broadband processor group, which is shipping a networking chip using HyperTransport. "The flexibility advantage is really big and the implementation baggage is really small," he said.
Competitors backing the RapidIO camp say they already support the new features the HyperTransport group is announcing and reject the need for legacy PCI capabilities. "This is all stuff that has been in RapidIO from the start," said Dan Bouvier, RapidIO vice chairman and PowerPC architect at Motorola. "I'm not sure how well they will be able to retrofit this into their existing designs."
The comms extensions will be rolled into a HyperTransport 1.x release this fall. The speed boost will not come until a broader 2.0 release early next year.
The group also plans a compliance testing program that may include setting up a testing agency and logo program. "That's one thing we are considering," said Keller.
But a plan to add coherency to the interconnect for multiprocessing implementations has generated competing proposals in the group. "There are a number of proposals floating around for what we are trying to achieve with coherency. There are different views on what we ought to be doing here," said Keller, who could offer no specifics on the time for concluding that work.
AMD has developed a coherent version of HyperTransport that will be used as the p rocessor bus for its Hammer CPUs coming early next year. But that approach may not need to be reflected in the standard, said analyst Brookwood.
Motorola's Bouvier said Hammer uses a snooping protocol that "leaves some performance on the table" when compared with a directory-based coherency scheme adopted by RapidIO.
The PCI Express interconnect, led by Intel, will also get extensions to make it more suitable for comms systems. A working group of companies is now quietly hammering out that spec, initially called 3GIO Advanced Switching, and expects to complete its work before August.
That group had briefly held discussions with the RapidIO camp about finding a path to interoperability. "They had been on again and off again. The steering committee at RapidIO decided to break off the talks," said Tom Cox, chair of the RapidIO marketing group.
"We had a lot of discussion on this and decided teaching Intel how to design this Advanced Switching to look like RapidIO was not in our charter," said Sam Fuller, president of the RapidIO trade group.
Intel was not immediately available for comment.
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