Virage Logic Corp. hopes to parlay its leadership in the market for licensable embedded memory into a position within a couple of years as one of the top three IP suppliers.
"That's a bold statement, but remember that three or four years ago people didn't believe we could exist as an independent company," said Adam Kablanian, president and chief executive of Virage Logic, Fremont, Calif.
Gartner Dataquest ranked the company as the second-fastest-growing IP vendor in 2001, behind Parthus. Virage Logic posted revenue of $31.7 million, a 61% increase from $19.6 million in 2000. It expects to generate $45 million this year, Kablanian said.
While the IP business model as a whole still has its share of detractors, two fundamental trends are working in Virage Logic's favor. One, the move by top foundries and their customers to standardize manufacturing processes will make it easier for IP suppliers to effectively address a wide base of foundry cu stomers.
"Today, our biggest competitors are the internal design teams at [integrated device manufacturers]," Kablanian said. "Process alignment is helping our cause in a big way, because now we can port our memories [to a new process] before internal design teams can start to develop it."
Two, the growing use of multiple processor designs will drive up average SoC memory content this year to more than 50%, according to the Semiconductor Industry Association.
To address this trend, Virage Logic last week at the Embedded Processor Forum in San Jose unveiled a high-speed multiport buffer memory architecture to increase data throughput in multiprocessor SoCs.
The SRAM-based Custom-Touch Area, Speed and Power (ASAP) embedded memory increases data throughput by up to 95% without increasing die size, said Krishna Balachandran, director of product marketing at Virage Logic.
The ASAP memory is the first embedded memory commercially available at mainstream foundries that can instantly configu re the number of read and write ports, saving months of design time, he said.
By allowing simultaneous access to different locations in the same memory, the reconfigurable ASAP devices eliminate the need for multiple register files, extra logic, and custom solutions, Balachandran added.
A single embedded ASAP memory provides up to 72Kbits of buffer memory and a total of six read and write ports. A user-controlled double-data-rate option allows for a read and a write operation at the same address during the same clock cycle by using both clock edges.
The ASAP embedded memory is available in Taiwan Semiconductor Manufacturing Co. Ltd.'s 0.13-micron process. Licenses start at $36,000.