Bytom -- January 3rd, 2013 -- Serial Peripheral Interface – Master/Slave with not only single and dual but most of all quad SPI Bus support, is the newest IP Core introduced by Digital Core Design. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. IP Core supports all 8, 16, 32 bit processors and has been designed to offer the fastest available operations for any serial memory.
The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device with data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. This quad SPI has been designed to offer the fastest available operations for any serial memory. Moreover the DQSPI has been design to operate with every 8, 16 or 32 bit processor available on the market.
The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. - In the Single SPI mode data is simultaneously transmitted and received – says Jacek Hanke, CEO in Digital Core Design - in DUAL and QUAD SPI modes – data is shifted in or out on respectively two or four data lines at once.
Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support interprocessor communications.
A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple‐master mode‐fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ re-quirements. More information: www.dcd.pl