Zagreb, Croatia -- January 7, 2013 -- New logiSPI SPI to AXI4 Controller Bridge IP core from Xylon's logicBRICKS™ IP library enables easy inter-chip board-level interfacing between virtually any microcontroller (MCU) and Xilinx® Zynq™-7000 All Programmable SoC and FPGAs through the Serial Peripheral Interface (SPI) bus. The SPI is a full-duplex synchronous four-wire serial interface between a single bus master, and one or more bus slave devices.
The logiSPI works as a SPI Slave controller and a 32-bit master controller on the ARM® AMBA® Advanced eXtensible Interface (AXI4) on-chip bus. The logiSPI IP core accepts and decodes a number of command SPI telegrams and allows the MCU to control peripherals implemented in the Zynq-7000 SoC or FPGA, or communicate with on-chip processors. Implemented bursting mechanism allows for large (2Kbytes) data transfers between on-chip and off-chip memories controlled by Xilinx programmable devices.
The logiSPI SPI to AXI4 Controller Bridge IP core is designed for use mainly in embedded systems that use the FPGA as a co-processor that adds missing host processor (MCU) features or offloads high-speed processing tasks. For example, system designers can use the logiSPI IP core to control complex graphics and video FPGA co-processor by a legacy MCU, or to add an additional SPI controller to the Zynq-7000 AP SoC design...
Xylon delivers the logiSPI IP core in a format which is fully compatible with Xilinx Platform Studio (XPS).
The logiSPI IP core license fees offered through Xylon's Low-Volume IP Program (LVIP) start at €650 (around $850). Free evaluation IP core is available for download.
For datasheet and general information about the logiSPI SPI to AXI4 Controller Bridge IP core please visit:
The logiSPI IP core can be evaluated on Xylon's logiCRAFT-CC Companion Chip Kits, or third-party hardware platforms.