CoWare Software Automates Hardware/Software Co-Design of MIPS-based™ SOCsSANTA CLARA, Calif., MOUNTAIN VIEW, Calif., TOKYO, May 13, 2002 -- MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB) and CoWare™, Inc. today announced an agreement that is structured to get new MIPS-based™ SOC (system-on-chip) designs to market faster by cutting design time and streamlining hardware and software development.
Under this agreement, the two companies will create a powerful new SOC design environment that integrates MIPS Technologies' higher level simulation models of the MIPS32™ 4KEc™, MIPS64™ 5Kc™, MIPS64 5Kf™ and MIPS64 20Kc™ high-performance processor cores and key peripherals into the CoWare N2C™ design system. Designers will be able to take advantage of CoWare's extensive system-level simulation and analysis tools to help determine the best bus architecture and hardware/software partitioning in order to strike the right balance between processor performance and overall system cost in terms of area or power. Designers also will be able to use CoWare's patented Interface Synthesis™ technology to automate the creation of hardware and bus interfaces as well as the software drivers, significantly speeding new designs to market and making trade-off analysis much easier.
"By teaming with CoWare, we can provide an environment that will help our customers determine how the MIPS32 or MIPS64 architectures can best meet their performance goals," said Brad Holtzinger, director of system solutions at MIPS Technologies. "With CoWare N2C, our customers are able to start at a high level of abstraction for HDL-based approaches. CoWare has demonstrated that its design environment can significantly reduce SOC design time. We're delighted to be working with CoWare to help bring this productivity improvement to our customers."
Alan Naumann, CoWare's president and CEO, added, "The MIPS architecture is used extensively in demanding, high-performance applications. By teaming with MIPS Technologies, we're broadening our solution scope to include the large base of MIPS developers. We're proud that our system-level design environment can meet the needs of MIPS Technologies' most advanced customers."
Determining the Best Architecture
Different architectures can make a tremendous difference in power and performance. In several cases, up to a 50-percent difference in performance has been noted between different hardware/software partitionings and architectures. The new CoWare design environment will allow designers to efficiently evaluate the industry-standard 32- and 64-bit MIPS® architectures to find the optimal trade-offs for the newest products in the networking and consumer device markets, such as set-top boxes, in-car entertainment, digital televisions and cameras, video game controllers, switches and routers, and office automation equipment.
This new integrated SOC design environment also will allow designers to more fully evaluate the effects of different hardware/software design trade-offs, analyze CPU loading, determine the optimum memory configuration, and make sure that the hardware and software continue to work together as the design is finalized.
Using Platform-Based Design to Speed Development
Designers will be able to use the design environment to develop a virtual platform so that software development can start earlier and concurrently with hardware design. As low-level drivers, middleware, operating systems and embedded applications are developed, this software can be verified with the hardware model.
The virtual platform also can be used to dramatically reduce the time needed to create derivative designs. By creating one "core" platform that can be extended in a variety of ways for different designs, companies can leverage their design investments several times over.
Promoting an Open Solution with SystemC™
The design environment integrates with most popular design and development tools. Any algorithm-design tool that outputs SystemC™ code, the de facto standard design language for system design, or ANSI C code can provide input to the design environment. For hardware designers, the design environment supports all of the popular register-transfer-level (RTL) simulators, both Verilog and VHDL, as well as leading RTL and behavior synthesis tools. For software developers, the design environment supports existing C/C++ design flows, including the import of existing libraries, and is compatible with the leading MIPS-based compilers, debuggers and RTOS tools.
CoWare and MIPS Technologies expect to complete the IP integration process necessary to make the new design environment available to customers starting in Q3 2002.
MIPS™ Alliance Program
CoWare has been a member of the MIPS Alliance Program (MAP) since 2000. MAP consists of premier third-party IP, development tool and application vendors who have ported their specific value-added products to MIPS architectures and cores for use in high-performance, state-of-the-art embedded systems.
As the leading supplier of tools for system-level electronic design automation (EDA), CoWare, Inc. provides a platform-based design methodology that can cut system-on-a-chip (SOC) design time in half. CoWare is driving the industry towards a unifying system design language as a founder and leader of SystemC. The CoWare software is employed by major systems, IP and semiconductor companies including Alcatel, ARM, Canon, Fujitsu, InterDigital, Matsushita, MIPS, Motorola, Nokia, Samsung, Sanyo, Sony, STMicroelectronics, Tensilica, Toshiba and Xilinx. CoWare was recognized as the 5th fastest-growing private company in Silicon Valley in 2000 by the San Jose Business Journal. For more information, visit www.CoWare.com.
About MIPS Technologies # # #
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.
CoWare, CoWare N2C and Interface Synthesis are trademarks of CoWare, Inc. MIPS® is a registered trademark in the United States and other countries, and MIPS-based™, MIPS32™, 4KEc™, MIPS64™, 5Kc™, 5Kf™and 20Kc™ are trademarks of MIPS Technologies, Inc. All other trademarks are the property of their respective holders.
Lee Garvin Flanagin
MIPS Technologies, Inc.
+1 (650) 567-5180
+1 (408) 845-7613
New Ideas in Communications for CoWare
+1 (650) 967-3711