IP Cores, Inc. announces more shipments of the cores from its LZR3 scalable lossless data decompression IP core family with very low decompression latency.
Palo Alto, CA -- January 22, 2013 -- IP Cores, Inc. announces more shipments of the cores from its LZR3 high-speed lossless data decompression IP core family with very low decompression latency.
"Our field-proven LZR3 family of IP cores supports scalable lossless data decompression with practically unlimited block size," said Dmitri Varsanofiev, CTO of IP Cores. "Scalability coupled with low latency allows the system designers, especially in the enterprise solid-state storage field, to avoid design trade-offs related to the higher latency inevitable in the cases when the scalability is achieved via the use of multiple low-performance decompression cores working in parallel.”
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. Lossless compression is used when it is important that the original and the decompressed data be identical, or when no assumption can be made on whether certain deviation is uncritical. Typical applications include data storage and communications.
LZR3 Family of Cores
LZR3 implements the lossless decompression on units of data (“blocks”). The core supports configurable maximum block with no practical limit (if necessary, the cores from the LZR3 family can decompress entire files). The design is fully synchronous and available in multiple configurations varying in throughput and bus width.
LZR3 can easily deliver tens of Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2.
LZR3 datasheet is available on the IP Cores, Inc. Web site.
About IP Cores, Inc.
IP Cores is a rapidly growing California company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 cryptographic hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi decoder cores.