English
Sidense Exhibiting at Common Platform Technology Forum
Update: Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation (Oct. 17, 2017)
Ottawa, Canada and Santa Clara, Calif. -- January 30, 2013
What
Sidense exhibiting at the Common Platform Technology Forum and presenting its 1T-OTP non-volatile memory IP spanning a wide range of process nodes (180nm to 28nm), including HV and BCD variants.
Where
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, California 95054
Booth 201
When
Tuesday, February 5, 2013
11:30AM to 6:00PM
Who
- Xerxes Wania, President and CEO
- Jim Lipman, Marketing Director
About Sidense
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. The Company’s innovative one-transistor 1T-Fuse™
architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (LNVM) IP solution. With 94 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in more than 250 customer designs, are available from 180nm down to 28nm and are scalable to 20nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit www.sidense.com
About the Common Platform Technology Forum
At the Common Platform Technology Forum, you will see and hear firsthand how the combined expertise of our partners is addressing the most demanding IC design and manufacturing challenges. Our collaborative research and innovative technology development have resulted in an accelerated roadmap and rapid customer adoption, and we'll touch upon these key highlights: leading-edge process technologies at 32/28-, 20-, 14-nanometer, and beyond; advanced innovations such as FinFet, design & technology co-optimization, and double patterning. You will get a peek into the future of next-generation device innovations being researched, including silicon nanowires, carbon nanotubes, and 3D device structures. Also visit the Partner Pavilion for a showcase of our Ecosystem Partner and Common Platform design, enablement, and implementation offerings. http://www.commonplatform.com/tf2013/
|
||||||
Related News
- Sidense Exhibiting at Common Platform Technology Forum
- Sidense Exhibiting and Presenting a Paper at the TSMC Open Innovation Platform (OIP) Ecosystem Forum
- Sidense Exhibiting its 1T-OTP Memory Solutions at TSMC Open Innovation Platform (OIP) Ecosystem Forum
- Sidense Exhibiting at TSMC Open Innovation Platform (OIP) Ecosystem Forum
- Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the TSMC 2024 Open Innovation Platform Ecosystem Forum
Breaking News
- Arm Total Design Ignites Growing Ecosystem of Arm-based Silicon for a Sustainable AI Datacenter
- Codasip unveils versatile automotive-grade embedded RISC-V core
- Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications
- CEA-Leti Launches OpenTRNG, an Open-Source Project For True Random Number Generators Using Ring-Oscillator-Based Architectures
- Agile Analog announces MoU to support new Southern Taiwan IC Design Industry
Most Popular
- September foundry sales: a tale of differing fortunes
- Intel, TSMC to detail 2nm processes at IEDM
- Arm, ASE, BMW Group, Bosch, Cadence, Siemens, SiliconAuto, Synopsys, Tenstorrent and Valeo commit to join imec's Automotive Chiplet Program
- SEMIFIVE Extends Partnership with Arm to Advance AI and HPC SoC Platforms
- DisplayPort Rx PHY and Controller IP Cores in multiple Leading Technology Nodes for Next-Generation Video SoCs
|
E-mail This Article | 
|
|
Printer-Friendly Page |