Cadence Releases Verification IP for USB SuperSpeed Inter-Chip Specification
SAN JOSE, Calif. -- 31 Jan 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced production-proven verification IP (VIP) for the new USB SuperSpeed Inter-Chip (SSIC) specification, enabling customers to thoroughly verify designs deploying the latest extension of the USB 3.0 protocol.
The SSIC specification combines the MIPI Alliance physical interface (M-PHY) with the upper layers of the USB protocol to enable USB 3.0 to connect chips within a mobile device. This makes it easier for mobile device manufacturers to leverage the large USB hardware and software ecosystem in the mobile environment.
"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol," said James Cheng, senior vice president, Global Unichip. "By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage."
"The SSIC extension of the USB 3.0 protocol is an important new tool for developers of mobile, smartphone and tablet devices because it offers higher data rates and power efficiency for internal use," said Martin Lund, senior vice president, research and development, SoC Realization Group. "Our USB 3.0 VIP has been used to verify over 100 designs, and we incorporated the knowledge gained to create this new product for engineers seeking the benefits of using the SSIC extension."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- MIPI Alliance and USB 3.0 Promoter Group Announce Availability of SuperSpeed USB Inter-Chip Specification
- Synopsys Demonstrates Industry's First SuperSpeed USB Inter-chip (SSIC) Interoperability
- PLDA Achieves IP Success with Cadence SuperSpeed USB (USB 3.0) Verification IP
- Mentor Graphics and Teledyne LeCroy Collaborate to Deliver New Emulation Verification Platform for SuperSpeed USB Applications
- SMSC Launches Industry's First, Hi-Speed Inter-Chip USB 2.0 to 10/100 Ethernet Controller for Low Power Applications
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |