Version 4 Speeds Performance and Enhances Coverage-Driven Verification
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 13, 2002--Verisity Ltd., the leading provider of functional verification automation, today announced the immediate availability of Specman Elite(TM) version 4. The latest release of Specman Elite features significantly improved performance, delivering about a 27 percent average speed improvement for compiled mode and about 15 percent for interpreted mode, enabling users to significantly shorten their verification whether using interpreted, compiled or mixed mode. In addition, Specman Elite v4 provides enhanced functional coverage analysis, including an integration with Verisity"s SureCov(TM) code coverage tool and new usability features including a generation debugger that enables users to view all aspects of the generation process.
"As designs grow ever more complex, it is crucial that verification tools keep pace," said Michael Mertz, director of product marketing for Verisity. "Specman Elite v4, with its significant performance improvements, an innovative new generation debugger and support for coverage-driven verification, continues to provide the means necessary to handle the verification of today"s most complex designs."
Specman Elite v4 provides several new coverage features that promote coverage-driven verification methodologies. New coverage features in v4 include:
- Integration with SureCov -- combines SureCov"s code coverage with Specman Elite"s functional coverage capabilities, enabling engineers to measure the effectiveness of their test plan and easily identify holes in both overall coverages, as well as, holes in the testplan itself.
- Coverage-per-instance -- enables users to measure and compare coverage of different instances of individual objects. This is particularly important in complex SoCs which often have multiple instances of buses, etc.
- Coverage extensibility -- provides more flexibility in defining and adding to the desired coverage base, enabling easy verification reuse of the coverage data from one design to the next. This is particularly useful in customizing the functional coverage of an eVC for a particular application.
- Coverage test ranking -- enables users to determine which tests give a high degree of coverage, per unit simulation time. With the new integration between Specman Elite and SureCov, this capability is available for functional, code or combined functional and code coverage.
"Our verification performance is significantly enhanced using Specman Elite v4," said Olivier Schuler, IP verification engineer for STMicroelectronics. "Verisity has also enhanced Specman Elite"s functional coverage features in v4 which makes it easier for us to obtain crucial coverage metrics for our verification efforts. Specman Elite v4 is an extremely powerful functional verification tool."
Specman Elite"s patented constraint-solving algorithms have made Specman Elite"s generator the most innovative in the industry. In v4, Verisity has created a new generation debugger to make it even easier to debug and understand how tests are being generated. The generation debugger enables users to view all aspects of the generation process and trace generation events by displaying key generation information graphically. This gives users the ability to quickly find and resolve issues that arise during generation.
Specman Elite v4 also contains many other new features including a data browser, a new memory manager and support for mixed hardware description languages (HDLs). The new data browser displays verification constructs graphically, easing navigation through the testbench data structures. The new memory manager provides robustness and fine-grain control over memory allocation during verification.
"Using the new memory manager in Specman Elite version 4 we built very memory-intensive packet generation code to generate long vectors of packets," said Greg Fife, principal verification engineer at Lucent IP Services Group in Westford, Mass. "This has made Specman Elite even better at creating datastreams that closely resemble real stimulus. In addition, we used the new data browser graphical user interface to examine data structures and list contents. These are very useful improvements in our verification flow."
Specman Elite v4 supports the following simulator interfaces from Verisity: the Verilog-XL(TM) simulator and the Affirma(TM) family of simulators (NC sim, NC Verilog, and NC VHDL) from Cadence Design Systems; the SpeedSim(TM) cycle-based simulator from Quickturn (a company of Cadence Design Systems); ModelSim from Model Technology; and VCS(TM) from Synopsys. Additional interfaces are available from Verisity"s VIP(TM) program partners.
Pricing and Availability
Specman Elite v4 is available now on the Linux Operating System, Solaris and HP workstations running HP-UX. The price is $50,000 U.S. for a floating LAN license.
Verisity is the leading provider of proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to high growth segments of the electronics industry. Verisity"s products simplify the process of detecting flaws in these designs, enabling customers to deliver higher quality products, accelerate time-to-market and reduce overall product development costs.
Verisity Design, Inc."s principal executive offices are located in Mountain View, Calif. The Company"s principal research and development offices are located in Rosh Ha"ain, Israel. For more information, see Verisity"s web site at www.verisity.com.
Verisity is a registered trademark of Verisity Design, Inc. Specman Elite, SureCov and VIP are trademarks of Verisity Design, Inc. All other trademarks are the property of their respective holders.
Verisity Design, Inc.
Jennifer Bilsey, 650/934-6823