Contributes to reduction of development time and cost
TOKYO -- February 14, 2013 -- Toshiba Corporation (TOKYO: 6502) today announced that it has introduced a new structured array that makes it possible to develop and deliver samples with a short turnaround-time, and that only requires the customization of a few layers of metal mask designs.
The new array uses technology licensed from BaySand Inc. and can create rich function, high performance, low power SoCs simply by customizing only a few metal mask layers. Compatibility with FPGAs can be achieved with verified RTL design data from the FPGA and shorten the turnaround-time for sample delivery to one-fifth that of conventional ASICs, to a minimum of just 5 weeks. Samples can also be delivered with the same pin layout as the FPGA. Another plus is that reducing the number of metal mask layers wins large reductions in the cost of NRE.
The new product uses 65nm process technology, with a 40nm line-up under development. Also, products with high-speed transceivers are under development, for each process.
- Able to create rich function, high performance, low power SOCs simply by customizing a few metal mask layer designs.
- Sample delivery with a short turn-around-time is possible (minimum 5 weeks) with verified RTL design data from an FPGA.
- FPGA pin layout compatibility allows use of existing circuit boards.
|Process Node ||65nm|
|Logic Gate ||Max 30M gates|
|SRAM ||Max 20Mbit|
|I/O pin ||Max 1200 I/O|
(LVDS, DDR available)
|RTL Hand-off ||Available|
|Mass Production ||Available from April 2013|
Outline of BaySand Inc.
- Company Name: BaySand Inc.
- Location: Morgan Hill, California, U.S.A.
- President: Salah Werfelli (President and CEO)
- Business: BaySand is a privately held fabless semiconductor company developing metal only configurable ASIC using its original Metal Configurable Standard Cell (MCSC) technology. It provides complete custom silicon solutions for FPGAs, standard-cell ASICs and customizable ASSP platforms.
- Web Site: http://www.baysand.com/